ASIC

 

• ASIC Design & Development Expertise for Diverse Applications
• Split Semiconductor Wafers
• What are Pilot Test Chips and Pizza Masks? 
• Transistor Semiconductor Process Selection f_T, f_u, f_max
• ASIC FIB
• Device Technology Push for mmW Bands
• Wafer Probe, Binning, and Wafer Map
• Delta Sigma Modulator, DSM
• Semiconductor Geometry, Moor’s Law Applicability
• HW Prototype vs. Reference Design
• Design for Manufacturability, DoM
• Design For Testability, DFT
• Shmoo Plot
• RF Amplifiers
• PLL & xCO
• DPD challenges for UWB signals 
• What is Dithering and why it is used? 
• What is Interleaving and Why it is used?
• Built In Self-Test, BIST
• Fractional N PLL
• PLL Requirements for Terrestrial Radio and Radar Applications
• UWB VCO
• Custom ASIC
• ASIC or Silicon Bring up
• Software Defined Radio, SDR
• What is SDR and why it is used?
• Semiconductor ASIC Life Cycle
• What is RF Limiter and how it is used?
• Digital Direct Synthesizer, DDS
• RF Circuit Design is about Impedance Matching
• AI Processor
• SERDES
• AI Neural Processor ASIC Requirements
• T/R Switch
• ARM Processor
• AI Edge Processor
• ASIC Design Flow
• 3 Reasons Why ASIC does not Sell?
• When first silicon is not successful?
• AI demands Processing in Memory
• Monolithic Microwave Integrated Circuit
• AI Processor ASIC Challenges
• From Model to Silicon: A Practical Framework for AI ASIC Decisions
• Reducing risk by aligning device physics with system and market requirements
• From Prototype to Product: The Role of Split Wafers in Commercial ASICs
• Startup Challenge Series — Foundation
• From Phase Noise to Dynamic Range: How PLLs Shape Radio and Radar
• From Wavelength to Impedance: Why RF Design Is an Impedance Problem, Not a Schematic Problem
• Managing Post-Tapeout Risk: The Role of FIB in ASIC Programs
• AI Doesn’t Need More Compute—It Needs Less Data Movement
• Choosing the Wrong AI Processor Is an Expensive Mistake
• Wafer Maps Don’t Lie: How Yield Decisions Are Really Made

 

ASIC Design & Development Expertise for Diverse Applications

From translating business requirements into clear technical specifications to delivering full custom ASIC solutions, ORTENGA provides end-to-end semiconductor design support.

Our team of seasoned engineers brings deep experience across  Autonomous Automotive, SATCOM, Radar, Smart City, WiFi, and Mobile Terrestrial Radio Communications Systems.

We help businesses define the technical features needed to achieve their product and market goals—ensuring each ASIC design is optimized for performance, power, and cost.

 

Split Semiconductor Wafers

ASIC is fundamental of many high-volume engineering solutions for commercial products.

Any product is either part of a larger system or it is actually a system.

All systems or even subsystems are comprised HW, FW, and SW.

The overall system performance is dependent on these components, HW, FW, and SW.

For a laboratory prototype device to be called an actual commercial product, it has to not only be functional but also meet specifications/system requirements over part-to-part aka process, voltage, temperature wide variations, better known as P.V.T. in the semiconductor industry.

A device that cannot handle cold or hot temperature is just a prototype, or proof of concept, and would not see commercialization daylight to return the investment.

To become commercial product, any device must be functional and meeting performance over P.V.T.

Split semiconductor wafers are intentionally altered during the engineering semiconductor fabrications in a such way that they mimic chemical variations which are typical for ASIC-to-ASIC variations of semiconductor fabrications during production phase.

The split semiconductor wafers are typically designed for at least 3 production speed variations, Slow, Nominal, and Fast.

The speed is associated with gate or transistor electron conductions performance.

Regarding RFIC, the semiconductor speed impacts gain which in turn the noise figure and non-linearity in the receiver chain.  The speed impacts output power and non-linearity in the transmitter chain.

Regarding SoC, the semiconductor speed impacts the switching speed which in turn the data throughput handling of the SoC.

ORTENGA helps businesses to identify required technical features to realize their business goals.

Partner ORTENGA in your next product concept, design, and development to realize that business goal.

ORTENGA has seasoned engineering from Autonomous Automotive, SATCOM, radar, Smart City, and Mobile Terrestrial Radio Communications System industries in ASIC, HW, FW, and SW engineering disciplines.

 

What are Pilot Test Chips and Pizza Masks? 

Application Specific Integrated Circuits, aka ASIC, are high volume electronic circuits which provide functionality of some portion of communications and/or radar systems. One of major cost components of these ASIC, is semiconductor mask.  Semiconductor masks are used for lithographically fabricating the semiconductor devices onto wafer.  Each wafer requires multiple masks for various layers of fabrications and etching. A typical vanilla CMOS process could easily have 200 masks or more and they could easily cost as much ~$3M depending on the geometry and size of the gates.

Each all layer revisions of ASIC require all ~200 masks; therefore it becomes prohibitively expensive for smaller companies or even big corporations to tape out any design for single project/product.

In order to save cost for any trial of ASIC before design is finalized, it is customary to run some pilot test chips to validate the design as well as the process performances.  For test chips run, it should only be enough number of them to be validated and characterized for desired performances, KPI.

Therefore, many semiconductor fabrications offer Pizza Mask, where number of companies can share the cost for the masks, ~$3M, and get only small portion of wafer area, “pizza”.  Very large corporations typically have their own pizza masks for multiple internal projects, test chips.  Or tandem with another project masks for couple hundred devices.

Each wafer lot is typically 25 wafers, and small portion of pizza/wafer, can produce few hundred devices per lot, enough to validate design topology and performance metrics.

Augment ORTENGA in your semiconductor device design and developments to utilize cost saving proven techniques which are not only benefits R&D cost, but also improves TTM, hence ROI.

 

Device Technology Push for mmW Bands 

CMOS technology has been the technology of choice for baseband digital and mixed signaling for number of decades.  In that past decade, CMOS was utilized for some of RF transceivers.

As radio transceivers go into mmW bands, the use of CMOS for RF signaling becomes limited and III-V compound technology are required to meet the specifications.  The following chart illustrates the Maximum Stable Gain, MSG comparison for CMOS vs. III-V compound technologies over the next few years.

ORTENGA has seasoned engineering from Autonomous Automotive, SATCOM, radar, Smart City, and Mobile Terrestrial Radio Communications System industries in ASIC, HW, FW, and SW engineering disciplines.

 

Transistor Semiconductor Process Selection f_T, f_u, f_max

f_T, Transition frequency is the transistor highest frequency where the current gain is unity or 0 dB, beyond this frequency there is no current gain.

f_max, maximum frequency is the transistor highest frequency where the unilateral gain becomes unity or 0 dB, beyond this frequency there is no power gain.

Many useful circuits require either current, voltage, or power gain.

As the application of radio frequencies increases, the required transistor’s f_T increases too.

For given semiconductor process, the gain slop is negative with 6dB/Octave or 20dB/decade in frequency.

Silicon processes’ f_T is a technical driver and depending on required “gain” or applicability a process is down-selected.

Obviously, cost is another driver for down-selecting the semiconductor process.

The cost of wafer drives the cost of ASIC.

The cost of wafer depends on the size of the wafer, the semiconductor process, and the number of lithography masks, which together drive the die per wafer cost.

As the wafer size increases, the number of dies per wafer increase, therefore ASIC cost decreases.

The silicon wafers, CMOS process in particular could be as large 15” diameter nowadays.

Higher radio frequencies’ circuitry requires III-V compound semiconductor process with higher f_T, such as GaAs, GaN, InP, etc.

The III-V wafers could be as large as 8” diameter nowadays and they are fewer fabs that can develop them.

The III-V compound semiconductors are typically used for applications with high RF performance which are less cost sensitive, such as; advance radio, radar, space, or specialized and custom-made radio front ends.

Furthermore, ASIC cost depends on wafer yield, wafer probe test time, packaged ASIC test time, and the package itself which could be significant portion of the total cost.

The wafer yield impacts the cost of ASIC and depends on circuit design topology and implementations as well as selected process tolerances.

Partner ORTENGA to succeed in your design and product delivery to the market.

ORTENGA has seasoned engineering from Autonomous Automotive, SATCOM, radar, Smart City, WiFi, and Mobile Terrestrial Radio Communications System industries in Antenna, ASIC, Algorithm, HW, FW, and SW engineering disciplines.

 

ASIC FIB

ASIC design and development go through multiple design reviews from early stage until tapeout.

During tapeout schematic vs. layout should be compared and any discrepancy should be carefully resolved.

Still, there are miscommunications and simple overlook occur.

These errors cause functionality at most and sometime performance issues only.

Functionality issues are the one where the circuit does not function at all.

Whereas performance issues are the one where the circuit functions yet do not meet all some performance metrics.

Functionality issues prevent any evaluation of the circuit.

Given ASIC tapeout expenses and timeline to fix any functional issue, there could be alternative option, FIB.

Focused Ion Beam, FIB allows to alter some changes to top layer of silicon for debugging and testing.

The easiest changes are to the metal layer connectivity.

ORTENGA helps businesses to identify required technical features to realize their business goals.

Partner ORTENGA in your next product concept, design, and development to realize that business goal.

ORTENGA has seasoned engineering from Autonomous Automotive, SATCOM, radar, Smart City, WiFi, and Mobile Terrestrial Radio Communications industries in Antenna, ASIC, HW, FW, and SW engineering disciplines.

 

Wafer Probe, Binning, and Wafer Map

Semiconductor wafers go through a long and costly expenses to be developed during production phase of any wafer lot.

The turn-around time is typically anywhere between 30 to 60 days depending on the process and fab house.

After the completion of the wafer lot, they go through wafer probe for design and process validations.

This testing occurs with Automatic Test Equipment, ATE which are similar to robot with testing capabilities.

Each wafer has thousands of Dies, i.e. ASIC, which would be tested individually.

A good die would pass all expected wafer test, Bin 1.

On the other hand, the bad dies are binned for various failures.

For instance, a die may fail for merely parametric of a single parameter marginally, Bin 2, while another die fails simple drawing current, Bin 99.

An electronic record of these failures with various bin numbers will be saved and called Wafer Map and will be passed on to the next step.

The next step is wafer dice and sort each bin number separately.

Obviously, Bin 1 Dies will be used for packaging.

Other Bins have to be analyzed if improving yield or root cause analysis is desired.

The yield impacts the cost of die per wafer.

ORTENGA has seasoned engineering from Autonomous Automotive, SATCOM, radar, Smart City, WiFi, and Mobile Terrestrial Radio Communications System industries in Antenna, ASIC, Algorithm, HW, FW, and SW engineering disciplines.

 

Delta Sigma Modulator, DSM

Ultra wide bandwidth data converters, ADC and DAC are becoming required for many applications, such as; advanced radio communications and radar systems.

UWB data converters enable monitoring/generating multiple signals within the overall system whether that is radio communications or radar applications.

In radio communications, the faster response time translate to shorter processing time for multiple signals.

In radar, the faster response time translate to shorter time to be aware of multiple targets.

DSM architecture can be configured for high resolution and low noise for UWB applications.

ORTENGA works with client and stakeholders to identify goals and deliverables of the project.

ORTENGA helps businesses to identify required technical features to realize their business goals.

Partner ORTENGA in your next product concept, design, and development to realize that business goal.

ORTENGA has seasoned engineering from Autonomous Automotive, SATCOM, radar, Smart City, WiFi, and Mobile Terrestrial Radio Communications System industries in Antenna, ASIC, Algorithm, HW, FW, and SW engineering disciplines.

 

Semiconductor Geometry, Moor’s Law Applicability

 

Digital circuitry relies on switching transistors, binary logic, 0 and 1.

Switching technology is directly proportional to semiconductor geometry.

Therefore, by reducing the geometry, the switching technology shrinks.

The size reductions have two impacts, the cost by increasing die per wafer, as well as reducing sleep current/power consumption.

Waveform generation and waveform analysis occur in digital circuits.

DSP is implemented by digital circuits with FPGA or equivalent processor.

The actual information is embedded in the digital waveform.

Analog circuitry, in particular, RF circuits are comprised of capacitors, inductors, as well as amplifiers.

It is only the amplifiers which utilize transistors and are relatively few comparing to digital circuits.

The inductance and capacitance values depend on semiconductor/silicon area and relative dielectric and permeability constants therefore their size does not scale with semiconductor geometry.

In reality the RF circuits scale with wavelength (frequency), therefore at operational frequencies the RF circuitry is small portion of the overall system, i.e., Digital, Mixed Signal, Analog circuits.

It is only signal conditioning and integrity of EM waves (carrier) which occur in the RF circuits.

ORTENGA helps businesses to identify required technical features to realize their business goals.

Partner ORTENGA in your next product concept, design, and development to realize that business goal.

ORTENGA has seasoned engineering from Autonomous Automotive, SATCOM, radar, Smart City, WiFi, and Mobile Terrestrial Radio Communications industries in Antenna, ASIC, HW, FW, and SW engineering disciplines.

 

What are the differences between HW Prototype and Reference Design? 

There are two types of HW projects; first Prototype, second Reference Design.

They are both similar yet with somewhat different objectives.

In case of HW Prototype, although there is some analysis and simulation, but the functionality and performance of the HW has never been verified.

This typically applies to out of box and innovative ideas and design validation which is required. HW Prototype is also used to characterize the design/device over Process, Voltage, and Temperature, aka PVT.

On the other hand HW reference design implies that there is confidence and supporting PVT data on the performance of the design, via HW Prototype.

The HW reference design is final product that external customer can acquire and validate them on their own.

The HW reference design is sometimes called the Evaluation Kit, aka Eval Kit.

Customer gets Gerber and Schematic files as well as design guidelines for duplicating the reference design.

Partner with ORTENGA in your HW design, development, and Bring up.

ORTENGA helps businesses to identify required technical features to realize their business goals.

Partner ORTENGA in your next product concept, design, and development to realize that business goal.

ORTENGA has seasoned engineering from Autonomous Automotive, SATCOM, radar, Smart City, WiFi, and Mobile Terrestrial Radio Communications industries in Antenna, ASIC, HW, FW, and SW engineering disciplines.

 

Design for Manufacturability, DoM

In general, any electronic circuit performance varies across Process, Voltage, and Temperature, PVT.

Process being circuit to circuit variations due to components’ tolerances, another words, part to part variations.

Applied voltage variations can impact the circuit performance.

Needless to say, temperature impacts the outcome of everything in the nature.

Furthermore, for RF circuits have frequency dependence.

Any manufacturable product must meet the product requirements over PVT.

Any device or product which does not meet the requirements, is technically not reproducible and failing devices would be returned by its customers.

That’s what differentiate a product from a prototype.

Prototype is not necessarily reproducible in volume, but demonstrates the concept behind its design.

Many companies fall into prototype which are not reproducible and cannot return the investment.

Partner with ORTENGA in your HW design, development, and Bringup.

ORTENGA helps businesses to identify required technical features to realize their business goals.

Partner ORTENGA in your next product concept, design, and development to realize that business goal.

ORTENGA has seasoned engineering from Autonomous Automotive, SATCOM, radar, Smart City, WiFi, and Mobile Terrestrial Radio Communications industries in Antenna, ASIC, HW, FW, and SW engineering disciplines.

 

Design For Testability, DFT

While testing any ASIC product occurs at the end of manufacturing cycle, the test could have far more implications on the return of the investment than originally planned.

A successful ASIC product which returns the investment has to meticulously budgeted for cost of every phase of its life cycle.

ASIC life cycle can be comprised of, product concept, ASIC requirements, design, manufacturing, and test.

Testing ASIC is the very last step in manufacturing before ASIC is shipped out the door, yet if testing methodology and requirements are not considered during the product concept, it could cost more or triggers many returns by the customers.

ASIC test cost is significant portion of overall budget and has to be carefully monitored.

To reduce the AISC cost and increase margin, the testing capability has to be studied and designed in such a way that it minimizes the testing time.

Minimizing ASIC test time is a challenging task which puts technical requirements on the ASIC design.

Design For Testability, DFT applies to highly complex ASIC which return the investment by taking into account testing methodology right up front in the design phase.

Many companies which did not integrate for DFT in their product life cycle, have fallen short in returning the investment.

Partner with ORTENGA in your HW design, development, and Bringup.

ORTENGA helps businesses to identify required technical features to realize their business goals.

Partner ORTENGA in your next product concept, design, and development to realize that business goal.

ORTENGA has seasoned engineering from Autonomous Automotive, SATCOM, radar, Smart City, WiFi, and Mobile Terrestrial Radio Communications industries in Antenna, ASIC, HW, FW, and SW engineering disciplines.

 

 

Shmoo Plot

Digital ASIC can be characterized at early stages for their performances, wafer probe via ATE.

The metrics of interest are functionality of logic gates over clock speed and Vcc.

The Shmoo plot is a quick health metric of digital ASIC.

ASIC performance can be done at various location on the silicon wafer or over various wafers to gain confidence on the measured data and statistical yield.

By tweaking some of the parameters, additional performance may be achieved.

The test stimuli for driving the digital ASIC are typically known as the test vector.

Test vector generation requires understanding not only the ASIC functionality but also designing appropriate vector and validating them before ASIC becomes available.

Time is of essence for commercial ASIC market to return the investment at an appropriate margin, therefore the sooner the ASIC is characterized and ready for production, the wider the margin.

Partner with ORTENGA in your HW design, development, and Bringup.

ORTENGA helps businesses to identify required technical features to realize their business goals.

Partner ORTENGA in your next product concept, design, and development to realize that business goal.

ORTENGA has seasoned engineering from Autonomous Automotive, SATCOM, radar, Smart City, WiFi, and Mobile Terrestrial Radio Communications industries in Antenna, ASIC, HW, FW, and SW engineering disciplines.

 

RF Amplifiers

RF amplifiers are used both in radio transmitter and receiver chains.

In the transmitter, there are two amplifiers, Drive Amplifier, DA and Power Amplifier, PA.

DA is typically post transceiver yet before PA, hence Drive Amplifier.

PA is the last amplification stage before the signal is delivered to antenna.

The objectives of both DA and PA are to amplify and increase the signal to adequate level before transmission into the air.

In the receiver chain, there are also at least two stages of amplifications.

Low Noise Amplifier, LNA is the closed amplifier to the antenna.  It is function is to amplify the small incoming signal yet at add very small amount of thermal noise.

It is less known to many that every electronic circuit add some noise to the signal and reduces SNR.  That applies to amplifiers too.

Trans-Impedance Amplifier, TIA is another amplifier typically after the frequency conversion and before ADC.  TIA could be known as IF amplifier.

Regardless of amplifier function, they are typically comprised of transistors active device for providing gain as well as input and output matching network.

What differentiate all of the above amplifiers, are two things.

First the transistor selected for gain or amplification.

Second the input and output matching network objective.

While the name may suggest the matching network job is to match the impedance.

The reality is different.

The matching network for LNA is noise match, while for PA is to power match.

In both cases the matching network is supposed to their job while keeping the circuit stable.

The stability is unspoken constraints yet implied and perhaps the most important requirement for any amplifier is to amplify not oscillate.

Typically, each gain stage can provide by up to 10dB gain, therefore multiple gain stages are needed to have larger gain amplifier.

Partner with ORTENGA in your HW design, development, and Bringup.

ORTENGA helps businesses to identify required technical features to realize their business goals.

Partner ORTENGA in your next product concept, design, and development to realize that business goal.

ORTENGA has seasoned engineering from Autonomous Automotive, SATCOM, radar, Smart City, WiFi, and Mobile Terrestrial Radio Communications industries in Antenna, ASIC, HW, FW, and SW engineering disciplines.

 

PLL & xCO

Phased Locked Loop, PLL and Voltage Control Oscillator, VCO are part of any ASIC whether it is analog, mixed signal, or digital circuits.

PLL and VCO provide Local Oscillator, LO functionality for any legacy Heterodyne and Homodyne radio front end.

PLL and Numerical Control Oscillator, NCO provide clock functionality for mixed signal and digital circuits.

In radio front end the PLL  and VCO phase noise contribute to noise budget and overall RF impairments of the radio which impact SNR.

Poor phase noise could desensitize and/or reduce dynamic range of the receiver.

Aperture jitter impacts Software Defined Radio, SDR SNR.

Jitter is time domain signature of phase noise in frequency domain.

ORTENGA helps businesses to identify required technical features to realize their business goals.

ORTENGA is comprised of seasoned and skillful engineers who collaborate on innovative design in entrepreneurial environment to accomplish clients’ project.

Partner ORTENGA in your next product PLL  ASIC design and development to realize that business goal.

ORTENGA has seasoned engineering from Autonomous Automotive, SATCOM, radar, Smart City, WiFi, and Mobile Terrestrial Radio Communications industries in Antenna, ASIC, HW, FW, and SW engineering disciplines.

 

DPD challenges for UWB signals

Digital Pre Distortion, DPD, technique is widely used in mobile UE to linearize Power Amplifier, PA, output signal, such that it can be run into saturation mode without violating spurious and unwanted emissions while mitigating transmitter power efficiency, hence increasing the battery life time.

It turns out that spectral efficiency and power efficiency have contradictory constraints.

As we pack more bits into one symbol or alphabet, higher QAM, then the signal becomes more spectral efficient, bit per second per Hz, bps/Hz, hence more throughput.  As a result, the Peak power to Average Ratio, PAR, between each symbol can change significantly.  Higher PAR requires higher linearity PA, which in turns requires higher power consumption, hence less power efficiency.

5G is targeting higher BW or user datarates; up to 100MHz for FR1 and up to 4GHz for FR2 bands.

What is Dithering and why it is used?

Dithering is a technique of reducing spurious unwanted signal which are unavoidable due to design architecture.

By modulating the unwanted spurious signal with wide band noise, the spurious signal can be reduced by several dB and in some cases suppressed below noise floor.

It is analogous to putting out fire by fire.

Dithering has applications in PLL, DSM, ADC, and DAC where spurious signals are number of one challenge for operational success.

Partner with ORTENGA for your PLL, DSM, ADC, and DAC design and development.

 

 

What is Interleaving and Why it is used?

Interleaving is the process of placing/shuffling bits within a symbol in such a way that decrease the chance of “Burst Errors” due to fading.

There are two class of interleaving, Block and Convolutional.

Block interleaving is when the symbol is written into row of a matrix and transmitted along the column of that matrix.

Pseudorandom Block interleaving is subclass and when the symbol is written into row of a matrix and transmitted in the pseudorandom mechanism.

Convolutional interleaving is when the symbol is multiplexed in and out of fixed number of shift registers.

Partner with  ORTENGA  to design and develop your new product.

 

Built In Self-Test, BIST

As integration level increases, not only testing methodology becomes more challenging, but also the cost of testing vs. scrapping components becomes prohibitive for volume production.

Built in self-test, BIST allows each major block to be designed for self-test and validation during manufacturing or even operations.

BIST is proactive methodology which takes into account the production cost as well as smooth operations.

BIST is applicable to PLL, Tx chain, Rx Chain, ADC, DAC, Antenna installation versification, Fault isolation, etc.

Partner with ORTENGA to design and development for your new product BIST.

 

Fractional N PLL

Phased Lock Loop, better known as PLL are used to generate Local Oscillator, LO for radio front end or Clock for baseband circuitry.

Clock to ASIC is similar to Heart to Body which drives and organize timing responses of various organs.  Without Heart, the body cannot function, without Clock the ASIC cannot function.

Fractional N PLL aka Frac N PLL has 3 main advantages over Integer N PLL.

1. Finer step frequency resolution relative to reference frequency
2. One Frac N PLL can provide LO function for both Tx and Rx chain
3. Agility to perform digitally controlled modulation

Needless to say, the above advantages do not come free, the Frac N PLL is much more complex in design and development.

In spite of that, the advantages overcome the trade off and are attractive in advanced ASIC.

Partner with ORTENGA to design and develop PLL ASIC.

 

PLL Requirements for Terrestrial Radio and Radar Applications

PLL phase noise requirements are driven by in band, IB and out of band, OOB drivers.

IB driver is dominated by desired channel purity requirements which has budget in overall SNR.

OOB driver is dominated by adjacent channel, typically considered undesired, which has budget in dynamic range of the system.

Dynamic Range, DR of a radio is measure of how the radio can handle both small desired signal in presence of loud unwanted signal.

SNR and DR of any system whether it is Terrestrial Radio or Radar are of significant concern and differentiators for end users.

Partner with ORTENGA to design and develop PLL ASIC.

 

UWB VCO

Ultra-Wide Band, UWB VCO are required in mmW and Radar applications.

Single VCO bandwidth circuitry is similar single element antenna bandwidth and can be quantified between 5 -10 % fractional bandwidth, FBW.

To increase the absolute bandwidth, the VCO frequency can be increased to 2x, 4x, or 8x of the required center frequency.

Consequently, post LO is frequency divided version of VCO.

Effectively that reduces the number of VCO for pulling full frequency range in UWB application, hence smaller ASIC die size, i.e., lower cost.

Octave or its multiple octave VCO resonance frequency helps with LO spurious free or purity of the desired spectrum.

These VCO provide mmW PLL functionality for mmW and Radar applications.

Partner with ORTENGA for frequency planning of UWB mmW and radar systems and VCO design and development.

 

Custom ASIC

ORTENGA has ASIC design and development capabilities now, in addition to Antenna and Algorithm design and development.

A radio communications or radar system has four major functional blocks, namely Antenna System Module, ASM, Front End Module, FEM, Transceiver Module, TRM, and Baseband Module, BBM.

Some of the mentioned blocks could be integrated into adjacent block or completely eliminated by choosing alternative architecture.  Nevertheless, a large number of legacy systems follow the above architecture.  ORTENGA tailors the above architecture to the client’s requirements for their application.

Historically, ORTENGA started with system architecture and definitions.

Then, ORTENGA enhanced its Algorithm development portfolio.

Typically, algorithms reside in FPGA.

ASM, FEM, and TRM functions are signal conversion and maintain signal integrity, whereas BBM function is to generate outgoing signals or detect and decipher the incoming signals within the MODEM.

Now, ORTENGA provides ASIC services for clients, either as a particular IP which can be integrated by the client into an IC or design and developing complete ASIC.

Over the past decade has grown and has end to end system design and development capability which can be tailored to many applications, such as; Autonomous Automotive, Radar, Smart City.

Partner with ORTENGA for design and development of your custom IP or ASIC that is tailored for your new product using seasoned engineering network.

 

ASIC or Silicon Bring up

Design and development of ASIC from concept to actual product goes through many phases.

Each phase requires specialized engineering skills that are challenging and takes considerable time to master.

Silicon or ASIC bring up phase to verify the design’s goal is no different.

Having silicon is not equivalent to having a prototype yet alone a product that can be manufactured in high volume for commercial applications.

Partner ORTENGA in design and development of your ASIC and silicon bring up to expedite time to market of your product and harvesting the return of the investment.

 

Software Defined Radio, SDR

Radio Communications Systems have many applications such as; Broadcasting, BT, RFID, SATCOM, Terrestrial, and WiFi.

Furthermore, Radar Systems have many applications such as; short and long range, search and tracking radar.

Each application chooses tailored architecture which are typically requires one or two frequency conversions from RF to IF for receiver and vice versa IF to RF for transmitter chain.

The frequency conversion module is needed to convert the data from its original format to transmittable format which is in radio frequency regions.

Frequency conversion block adds significant design burden which means, it can only support one application.  Any system that can work without the frequency conversion block is highly desirable in both Radio Communication Systems and Radar Systems.

Removing the frequency conversion could be done if high datarate digitizer and waveform can be created that allows broad bandwidth.

In any architecture, ASIC plays the key role to achieve system requirements and performances.

Partner with ORTENGA to design and develop ASIC and SDR Communications or Radar system.

 

What is SDR and why it is used?

Software Defined Radio, SDR is an architecture which frequency conversion are removed from the radio front end.

That means, the radio front end is comprised of antenna, amplifier, and frequency selective filter components.

The objective for removing the frequency conversion block from radio front end is to alleviate the dependency of frequency conversion block on utilized desired signal waveform.

Various Radio Communications or Radar systems require dedicated waveform.

SDR allows the Radio Communications or Radar systems to become compatible to various desired signal waveforms.  Consequently, SDR is desirable architecture.

Partner with ORTENGA to design and develop your SDR system or ASIC.

 

Semiconductor ASIC Life Cycle

Semiconductor ASIC has 2 years life cycle.

A successful ASIC  product would return the investment within that first 2 years.  After that the ASIC would need to be enhanced either with additional features, speed, power, cost, and/or size.

By then, if this successful ASIC is not upgraded, the competition would catch up and reproduce similar or additional features to gain some of the market share.

On the other hand, if the ASIC  is not successful in the market, it would automatically become obsolete and would not return that investment.

Partner with ORTENGA for feature definitions of your new ASIC, design and development,  or evaluate competitive landscape market.

 

What is RF Limiter and how it is used?

RF Limiters are used to protect sensitive electronic circuits, such as receivers’ front end, from strong undesired signal which can damage them.

Radio receivers are supposed to be very sensitive to very small desired signals of interest.

On the other hands, there are undesired signals which could be very large, 20 to 40 dB relative to the desired signals.

The receiver has job is to function in the presence of these types of undesired signals and yet survive that strong undesired signal.

This is particularly challenging when that desired signal is close to the top level of its dynamic range, consequently the strong undesired signal is way more than the level which receiver cannot function anymore.

Even though, we expect the receiver to survive this extreme radio environment condition.

The undesired signals could be due to un-intentional or intentional source.

Un-intentional source could be a radio station nearby or radar jammer which is trying to damage the radar system to avoid detection.

Partner with ORTENGA to design an develop radio front that can survive strong undesired signal while function detection without being compromised.

ORTENGA can design and develop limiter with hybrid passive and active electronic components to meet stringent requirements.

 

Digital Direct Synthesizer, DDS

Digital Direct Synthesizer, DDS are digitally controlled frequency synthesizer source.

DDS have gain traction for many applications because of:

• Excellent frequency resolution
• Excellent frequency agility
• Amplitude, frequency, and phase modulations capabilities
• Digitally controlled
• Size
• Cost

DDS are utilized in many Arbitrary Wave Generators, AWG.

As high speed and wide bandwidth DAC becomes a reality, DDS finds more traction for highly integrated low-cost frequency synthesizer.

SDR architecture relies on DDS.

Partner with ORTENGA for your DAC and DDS design and development.

 

RF Circuit Design is about Impedance Matching

When operating wavelength (frequency) is in order of electrical component size, KVL and KCL analysis fails as they are not applicable any longer, typically this is Radio Frequencies, RF.

Whether the architecture utilized is Heterodyne, Homodyne, or Software Defined Radio, SDR, there are LNA and PA in all these architectures.

LAN and PA designs are about impedance matching.  There is optimum yet distinct power gain, low thermal noise, high output power, and stable impedance regions.

Based on the design goals, the RF circuit designer needs to identify the above impedance and down select an optimum impedance for the input and output (and sometime inter-stage) in such a way that the overall performance meets stability and performance metrics.

Partner with ORTENGA for your RF circuit design and development.

 

AI Processor

Artificial Intelligence, AI processor function is to compute D = A x B + C with multiple dimensions matrix manipulations.

Typically, AI utilizes either Graphical Processor Unit, GPU, Neural Processor Unit, NPU, or Edge Processor Unit, EPU, or Tensor Processor Unit, TPU.

EPU is used for Edge device, such as Smart Phone that is power limited yet needs some AI capability, e.g. voice or image recognition.

TPU is used for high level of computations for multivariable input data or features, e.g. image processing.

Each processor is tailored for certain AI algorithm and its power consumption either within FPGA or AI ASIC.

Multi variable matrix, Tensor, manipulation order of computation, BUS speed, and High Bandwidth Memory, HBM are main drivers of ASIC accelerator design.

Partner with ORTENGA to analyze your product constraints, specify appropriate processor architecture to design and develop AI ASIC.

 

SERDES

Serial to De-serializer, SERDES plays a key role in AI data processing.

AI processor has to crunch massive amount of data.

The data goes between multiple chips or IP blocks within the ASIC.

Partner with ORTENGA for your AI design and development.

 

AI Neural Processor ASIC Requirements

Neural processor is a simple processor that performs single computation, e.g., addition, multiplication, etc.

Consequently, to execute a simple algorithm, thousands of neurons are required.

Therefore, to execute a tensor with large dimensions, millions of neurons are required.

As a result, the power consumption would become a limiting factor for real world problems, unless the following neuron behavior can be designed and met:

1. Zero power consumption for sleeping/unused neurons
2. Low amount of power for working neurons
3. Low complexity or low number of operations algorithms are designed and utilized

Partner with ORTENGA for AI Neural processor requirements, design, and development.

 

T/R Switch

Transmit and Receive, T/R Switches are utilized in radio front end system where Transmitting and Receiving occurs at a different time, e.g. TDD communication or radar systems.

TR switch typically resides right after antenna and requires high isolation between transmit and receive chain.

Needless to say, the switching speed has to be much better than the operating time interval.

Consequently, the switching time and isolation are the key driver in designing T/R Switch.

Silicon on Insulator, SoI is the process of the choice to meet both requirements.

In many system, the tolerance of the receive chain to withstand high power is another requirement which can be met via RF Limiter.

Partner with ORTENGA for T/R Switch design and development.

 

ARM Processor

Advanced RISC Machine, ARM processor is an advanced Reduced Instruction Set Computer, RISC.

RISC is designed for faster instructions execution, i.e. execution in HW as opposed to SW.

In addition, RISC is designed for lower power consumption, i.e. executing instruction per cycle.

The above two features are desired for Edge, Mobile, or battery-operated devices.

Partner with ORTENGA in your ASIC design and development.

 

AI Edge Processor

Artificial Intelligence, AI Edge relies on ARM processor architecture.

ARM processor architecture is known for its speed and low power consumption.

AI Edge processor requires even faster and lower power consumption compare to its ARM predecessors.

That implies faster and larger or deeper internal registers and Cache.

In addition, the AI Edge processor is required to consume lower power per instruction in comparison to its ARM predecessors.

If the required speed is more than what the semiconductor process can achieve, then multi-core processor is utilized to work in parallel and achieve higher throughput per instruction.

Partner with ORTENGA in your ASIC design and development.

 

ASIC Design Flow

For any radio or radar system to perform as expected, there has to be a clear use cases and expectations under which the system to operate.

The use cases define what the system is designed for.

The use cases are to fulfill the business goals or requirements and return of investment, ROI.

Therefore, the use cases are the intersection of business goals and system definition.

The radio or radar systems are composed of 3 distinct engineering disciplines, namely; Antenna, ASIC/HW, Algorithms /FW/SW.

The following ASIC design flow diagram illustrates the step in defining, designing, simulating, fabricating, and measuring ASIC performance in hierarchical manner to fulfill the system requirements and business goals.

Partner with ORTENGA for your ASIC design and development.

 

3 Reasons Why ASIC does not Sell?

ASIC design and development take many months and the manufacturing process is lengthy and expensive.  Yet many start-ups which are venturing in ASIC business fail to realize the challenges and burn valuable resources before coming to terms with these challenges.

1. About 2/3 of ASIC or any other product failure is lack of appropriate features in its market. This failure is typically due to not following proper ASIC Design Flow.  ASIC with missing feature does not meet the customer needs to begin with and therefore won’t sell.
2. About 1/3 of ASIC failure in the market is due to its cost. Electronic integration is supposed to be cost effective by definition.  If the cost of making the final product without that particular ASIC is less, then the ASIC won’t sell.
3. After the above, any ASIC failure in the market is due to its obsoleteness and irrelevant. If the ASIC has missed the market and is trying to compete with more mature ASIC or competitors which manufacture more elegant ASIC, then the ASIC won’t sell.

Here is how you could differentiate the issue with not selling ASIC.

1. If the ASIC gets customer traction yet, it falls through during the business arrangement, then it is the cost, therefore the number 2 above is the reason.
2. If the ASIC gets customer traction yet does not even make it to customer evaluation, then it is the lack of missing features, therefore the number 1 above is the reason.
3. If there is no customer traction, then the ASIC has missed its market.
4. If customers request for evaluation without asking for detailed evaluation data available from ASIC vendor, then the ASIC is first to the market without any known competitors to the customer. This is ideal situation for high margin ROI.

Partner with ORTENGA for new ASIC design and development which returns the investment.

 

When first silicon is not successful?

ASIC design and development is lengthy process and expensive.

Most companies without the experience of silicon design and development, if not all, underestimate the challenges.

Therefore, they fail to have the first silicon meet the market needs, which in turn not only increase the development cost but also the slipping away from the window of opportunity.

Here are the main reasons for not being successful at the first silicon article.

1. Lack of clear use cases definition
   2. Lack of design specifications locked down at the beginning of design phase
   3. Lack of designing to the specifications
   4. Lack of independent design audit

Incidentally, the above reasons apply to other electrical component design, such as Antenna.

Partner with ORTENGA for ASIC design and development.

 

AI demands Processing in Memory

Artificial Intelligence, AI requires processing large amount of incoming data.

One of the techniques to handle this large data between various ASIC is to utilize SERDES between ASIC.

The required SERDES is very high speed, 20 – 200 Gsps.

High speed SERDES is power hungry and power inefficient with current technology.

Legacy AI processor architecture accesses the large data from memory, RAM.

One way to reduce the AI processing power consumption is to remove the need for moving data from one ASIC to another.

By moving Arithmetic Logic Unit, ALU into the memory, RAM, significant amount of power can be saved.

Processing In Memory, PIM architecture is already implemented by Samsung and SK Hynix partnership.

Partner with ORTENGA in your new ASIC design and development.

 

Monolithic Microwave Integrated Circuit

Monolithic Microwave Integrated Circuit, MMIC is a circuit module which can be found in radio front ends of Radio Communications or Radar systems.

MMIC module could have Antenna, ASIC, or Algorithms via HW/FW/SW implementations.

ORTENGA helps businesses to identify required technical features to realize their business goals.

Partner with ORTENGA for your MMIC design and development.

ORTENGA has seasoned engineering from Autonomous Automotive, SATCOM, radar, Smart City, WiFi, Mobile Terrestrial Radio Communications, and 6G industries.

 

AI Processor ASIC Challenges

Artificial Intelligence, AI processors are in high demand for many new verticals, e.g. mobile or stationary processors.

Legacy processors are architected, designed, tailored, optimized, and suitable for human data queries and interactions.

AI processors are required to work with servers’ data centers, multiple sources on internet, and data queries by algorithms.  The amount of input data to the processor is greater by few orders of magnitude for even simple tasks or computations.

Using legacy processor architecture for AI related computations demand custom ASIC requirements which are challenging and power inefficient.

The AI processors require innovative processor architecture which is power efficient, fast, and small.

Partner with ORTENGA to design and develop AI processor ASIC.

 

From Model to Silicon: A Practical Framework for AI ASIC Decisions

Artificial Intelligence, AI ASIC are tailored solution for specific application.

The alternative solution is to utilize generic IC to run AI models.  That AI model running on the generic IC can be replaced with a completely different model which could have HW and IC implications.

This alternative solution is attractive from reusability perspective of the IC and HW.  The drawback of the alternative solution is over designing the IC and HW to support any AI model, therefor it is cost prohibitive for some partners and collaborators.

Smart solution is to conduct technical feasibility of the AI model for its application.  Once 80% confidence is reached, then investigate and document potential changes and upgrades for the down selected model.  Consequently, specify required IC and HW based on comprehensive AI model and its subsequent upgrades.

Partner with ORTENGA for AI ASIC design and development.

 

Save Millions on ASIC Development: ORTENGA’s Pilot Test Chips and Pizza Mask Approach

Application Specific Integrated Circuits (ASICs) are high-volume electronic circuits that provide critical functionality for communications and radar systems. One of the largest cost drivers in ASIC development is the semiconductor mask. Masks are used for lithographically fabricating the circuits onto wafers, with each wafer requiring multiple masks for various layers. In a typical CMOS process, this can easily involve 200+ masks, costing around $3 million depending on geometry and gate size.

Every full-layer revision of an ASIC requires all ~200 masks, making it prohibitively expensive for smaller companies—or even large corporations—to tape out a design for a single product.

Pilot Test Chips: Minimizing Risk, Maximizing Insight

To validate a design and process performance before committing to full production, it is customary to run pilot test chips. These small-scale test chips:

• Verify that the design meets intended functionality.
• Characterize performance metrics and KPIs.
• Identify potential design or process issues early, avoiding costly mistakes.

The goal is to produce only enough devices to validate the design, saving significant R&D costs while accelerating development.

Pizza Masks: Sharing Costs, Saving Millions

To further reduce costs, many semiconductor foundries offer Pizza Masks. Here, multiple companies share a single mask set (~$3M), each receiving a “slice” of the wafer. This approach allows:

• Small portions of a wafer to produce a few hundred test devices—enough for performance validation.
• Companies to reduce the upfront cost of full mask sets.
• Large corporations to run multiple internal projects using their own pizza masks or combine projects to maximize efficiency.

A typical wafer lot contains 25 wafers, making pizza slices more than enough for ASIC validation.

ORTENGA’s Expertise: Turning Cost Savings into Faster ROI

At ORTENGA, we augment your semiconductor device design and development with proven cost-saving techniques like pilot test chips and pizza masks. Our multi-disciplinary engineering team:

• Optimizes test chip layouts to minimize wafer usage.
• Helps select the most effective mask-sharing strategies.
• Ensures early detection of design or process issues to accelerate time-to-market (TTM).
• Maximizes ROI by reducing wasted silicon and avoiding expensive full-mask re-spins.

By leveraging ORTENGA’s expertise, your R&D efforts become more efficient, cost-effective, and agile, helping your project move from concept to silicon faster and smarter.

✅ Key Takeaway:
Pilot test chips and pizza masks are essential strategies to manage ASIC R&D costs. With ORTENGA’s guidance, companies can validate designs efficiently, save millions, and shorten time-to-market without compromising performance.

 

Reducing risk by aligning device physics with system and market requirements

 

Connecting device-level limits to system performance, yield, and time-to-market

Selecting the right semiconductor process for an RF or mixed-signal ASIC is fundamentally a tradeoff between frequency capability, gain requirements, yield, and cost. Two transistor figures of merit—f_T and f_max —sit at the center of this decision.

Understanding f_T and f_max

• f_T (Transition Frequency)
  f_T is the frequency at which the transistor’s current gain falls to unity (0 dB). Beyond this point, the device no longer provides current gain.
• f_max (Maximum Oscillation Frequency)
  f_max is the frequency at which the transistor’s unilateral power gain becomes unity (0 dB). Beyond f_max, the device cannot deliver power gain.

Different RF and mmWave circuits rely on current gain, voltage gain, or power gain, making both f_T and f_max critical—depending on the application.

Frequency Scaling and Gain Roll-Off

As operating frequency increases, required transistor performance rises accordingly. For any given semiconductor process, gain rolls off at approximately:

• –6 dB per octave, or
• –20 dB per decade

This fundamental behavior limits how far a given technology node can be pushed and directly influences process down-selection.

Silicon CMOS: Cost and Scale Advantages

In silicon CMOS processes, f_T is a key technical driver, but it must be evaluated alongside cost.

ASIC cost is strongly tied to wafer economics, including:

• Wafer diameter
• Process complexity
• Number of lithography masks

Larger wafers yield more dies per wafer, lowering the cost per die. Modern CMOS fabs routinely process wafers up to 300 mm (12”), with some advanced lines approaching even larger effective production formats. This scale advantage makes CMOS highly attractive for cost-sensitive, high-volume applications.

III–V Compound Semiconductors: Performance First

At higher RF and mmWave frequencies, silicon reaches its practical limits. Applications demanding extreme RF performance often require III–V compound semiconductor processes with much higher f_T and f_max, such as:

• GaAs
• GaN
• InP

These technologies support superior gain, breakdown voltage, and power density but come with important tradeoffs:

• Smaller wafer sizes (typically up to ~8”)
• Fewer qualified fabs worldwide
• Higher per-die cost

As a result, III–V processes are commonly reserved for less cost-sensitive, performance-driven markets, including:

• Advanced radio systems
• Radar
• Space and SATCOM
• Specialized or custom RF front ends

Yield, Test, and Packaging: The Hidden Cost Drivers

Beyond wafer cost, total ASIC cost is heavily influenced by:

• Wafer yield, driven by process maturity and circuit robustness
• Wafer probe test time
• Packaged device test time
• Package selection, which can represent a significant fraction of total cost

Yield, in particular, depends not only on the foundry process but also on circuit topology, layout discipline, and tolerance to process variation—areas where design experience has an outsized impact on commercial success.

From Device Physics to Product Success

Choosing the optimal semiconductor process is not about maximizing f_T or f_max in isolation. It requires a system-level understanding of:

• Required gain type (current, voltage, or power)
• Operating frequency and bandwidth
• Cost targets and production volume
• Yield and test strategy
• Long-term product scalability

Partner with ORTENGA

ORTENGA helps companies navigate these tradeoffs from silicon to system, ensuring that transistor-level decisions align with product-level outcomes.

ORTENGA brings seasoned engineering expertise across:

• Autonomous automotive
• SATCOM and space systems
• Radar
• Smart city infrastructure
• Wi-Fi and mobile terrestrial radio

Our network spans Antenna, ASIC, Algorithm, Hardware, Firmware, and Software engineering, enabling predictable execution—from process selection through product delivery.

ORTENGA aligns transistor physics with system requirements and product economics.

Antenna • ASIC • Algorithm • HW • FW • SW
Autonomous • SATCOM • Radar • Smart City • Mobile Radio

 

From Prototype to Product: The Role of Split Wafers in Commercial ASICs

Designing for P.V.T. Corners to Ensure First-Silicon and Market Success

1. ASICs as the Foundation of Commercial Systems

ASICs are the backbone of many high-volume commercial products. Every product is either a complete system or part of a larger system, and every system is composed of hardware (HW), firmware (FW), and software (SW).

The performance, reliability, and commercial success of a product depend on how well these elements function together—not only in the lab, but in real-world conditions.

2. Why Functional Prototypes Rarely Equal Commercial Products

A laboratory prototype that works under nominal conditions is only a proof of concept.

To qualify as a commercial product, an ASIC must:

• Meet specifications across process variations
• Operate reliably over voltage tolerances
• Perform across temperature extremes

This is known as P.V.T. (Process, Voltage, Temperature) variation. Devices that fail under cold, hot, or voltage-stressed conditions never reach production and never return investment.

3. Understanding P.V.T. Reality in Semiconductor Manufacturing

No two ASICs coming off a production line are identical. Natural manufacturing variations cause each die to behave slightly differently.

Ignoring these variations leads to:

• First-silicon failures
• Costly re-spins
• Missed market windows
• Long-term reliability issues in the field

Engineering for P.V.T. is not optional—it is a prerequisite for commercialization.

4. What Are Split Semiconductor Wafers?

Split semiconductor wafers are intentional engineering fabrication variants used to emulate real production variability.

During an engineering run, wafers are processed with controlled changes in:

• Transistor dimensions
• Doping concentrations
• Threshold voltages
• Gate performance

These splits allow engineers to observe how silicon behaves before volume production begins.

5. Silicon Speed Corners: Slow, Nominal, and Fast

Split wafers are typically designed to represent three fundamental silicon performance corners:

• Slow silicon – reduced carrier mobility and lower switching speed
• Nominal silicon – expected typical performance
• Fast silicon – higher carrier mobility and faster switching speed

These speed variations directly correlate to transistor and gate electron conduction performance.

Diagram description:
A circular semiconductor wafer divided into regions labeled Slow, Nominal, and Fast, visually representing intentional process splits used to emulate production variability.

6. Impact of Silicon Speed on RFIC Performance

In RFICs, silicon speed variations have cascading system-level effects:

• Receiver chain
  • Gain variation
  • Noise figure degradation
  • Linearity challenges
• Transmitter chain
  • Output power variation
  • Non-linearity and spectral regrowth
  • Efficiency trade-offs

A design that works only at nominal silicon speed is not production-ready.

Diagram description:
Plots showing gain, noise figure, and linearity trends across Slow–Nominal–Fast silicon corners.

7. Impact of Silicon Speed on SoC Performance

For SoCs, silicon speed directly impacts:

• Logic switching speed
• Timing closure
• Maximum clock frequency
• Data throughput capability

Slow-corner silicon often exposes:

• Setup/hold timing violations
• Marginal interfaces
• Reduced system margins

Designing only for typical conditions guarantees surprises in production.

Diagram description:
A timing margin or throughput envelope illustrating how Slow, Nominal, and Fast silicon affect SoC performance limits.

8. Why Split Wafers De-Risk First Silicon

Split wafer analysis allows teams to:

• Validate margin early
• Tune biasing and control loops
• Adjust architecture before mass production
• Prevent expensive post-silicon redesigns

This directly improves first-silicon success rates and reduces overall program risk.

9. Translating Business Goals into Technical Requirements

Many ASIC failures are not technical—they are misaligned business and engineering decisions.

Commercial success requires:

• Early definition of use cases
• Clear performance margins
• Design targets aligned with deployment environments
• Engineering decisions informed by manufacturing reality

10. How ORTENGA Enables Commercial-Ready ASICs

ORTENGA helps businesses identify the technical features and margins required to achieve business objectives, not just lab success.

By engaging early in concept, architecture, and design phases, ORTENGA helps ensure products are engineered for:

• P.V.T. reality
• Manufacturing scalability
• Market timing
• Investment return

ORTENGA brings seasoned engineering expertise from:

• Autonomous Automotive
• SATCOM
• Radar Systems
• Smart Cities
• Mobile and Terrestrial Radio Communications

with deep capabilities across ASIC, HW, FW, and SW disciplines.

 

Startup Challenge Series — Foundation

Designing ASICs from Business Goals to Measured Silicon

A Silicon-to-System Execution Framework

Why This Is Foundational

Before startups struggle with first-silicon failures, integration surprises, or schedule slips, they encounter a more fundamental problem:

They design ASICs without a system-level, business-anchored execution model.

This framework establishes the reference architecture that all subsequent Startup Challenges build upon. Every challenge that follows—whether technical, organizational, or financial—can be traced back to a breakdown in one or more stages of this flow.

The Core Insight

Use cases are not technical artifacts.
They are the translation layer between business goals and system behavior.

When that translation is weak, ASICs may meet block-level specifications, pass simulations, and fabricate successfully—yet still fail to deliver system value or ROI.

Figure 1 — Silicon-to-System Execution Framework
(Full-width visual showing traceability from Business Goals → System Use Cases → System Requirements → ASIC Execution → Measurement & Correlation, with closed-loop feedback)

The Silicon-to-System Execution Flow

This framework enforces continuous traceability across five layers:

1. Business Goals & ROI
   Market, cost, schedule, deployment constraints
2. System Use Cases
   Quantified operational scenarios and success conditions
3. System Requirements
   Antenna, ASIC / Hardware, Algorithms / Firmware / Software
4. ASIC Execution
   Design → Simulation → Fabrication
5. Measurement & Correlation
   Measured silicon mapped back to system KPIs and business intent

Each layer exists to prevent early assumptions from becoming late-stage failures.

Why This Matters

Most first-silicon failures are not caused by transistor-level mistakes.
They originate from misalignment between business goals, system requirements, and ASIC execution.

When that misalignment is discovered after fabrication, correction is slow, expensive, and often market-fatal.

ORTENGA’s Role

ORTENGA is not a staffing firm and not a design house.

We operate as an execution partner at the highest-risk transition points—from business intent to system definition to silicon reality. By enforcing traceability across business goals, system use cases, and ASIC implementation, ORTENGA reduces execution risk before it becomes expensive and irreversible.

ORTENGA exists to ensure that every ASIC decision remains traceable—from business goals to measured silicon—so execution risk is reduced before it becomes irreversible.

 

From Phase Noise to Dynamic Range: How PLLs Shape Radio and Radar

Why in-band and out-of-band phase noise must be architected from system requirements, not just silicon

Phase-locked loop (PLL) phase noise requirements in terrestrial radio and radar systems are driven by in-band (IB) and out-of-band (OOB) considerations.

In-band (IB) phase noise is primarily dictated by desired channel purity. Its impact is directly budgeted within the overall signal-to-noise ratio (SNR), influencing demodulation accuracy, bit-error rate, and detection sensitivity.

Out-of-band (OOB) phase noise is dominated by adjacent and nearby undesired signals. These components stress the dynamic range (DR) of the system by raising the effective noise floor in the presence of strong blockers.

Dynamic range describes a radio or radar system’s ability to reliably detect weak desired signals while simultaneously tolerating strong unwanted interferers. It is a critical performance metric for both terrestrial communication and radar platforms.

Together, SNR and DR are foundational system-level differentiators. They define real-world performance, robustness, and ultimately user experience—often more than peak data rate or raw output power.

Partner with ORTENGA to design and develop PLL ASIC solutions that are architected from system requirements backward, ensuring phase noise performance is aligned with end-application SNR and dynamic-range constraints—from silicon to system.

 

From Wavelength to Impedance: Why RF Design Is an Impedance Problem, Not a Schematic Problem

How Distributed Effects, Matching Tradeoffs, and Stability Define Real RF Performance

When the operating wavelength becomes comparable to circuit dimensions, classical circuit assumptions break down. At radio frequencies (RF), lumped-element analysis based on KVL and KCL no longer tells the full story. Distributed effects dominate, parasitics become first-order contributors, and impedance—not schematics—becomes the governing design variable.

This is why RF systems often fail in ways that are difficult to diagnose. A schematic can be “correct,” simulations can converge, and yet measured performance still misses noise figure, gain, linearity, or stability targets. The root cause is rarely a missing component—it is almost always an unexamined impedance tradeoff.

Regardless of architecture—heterodyne, homodyne, or software-defined radio (SDR)—every RF signal chain relies on low-noise amplifiers (LNAs) and power amplifiers (PAs). These blocks do not have a single optimal impedance. Instead, there are distinct impedance regions for:

• Maximum available or transducer gain
• Minimum noise figure
• Maximum output power and efficiency
• Conditional or unconditional stability

Critically, these regions do not coincide.

Effective RF design is therefore an exercise in compromise. The designer must identify these impedance regions and deliberately down-select input, output, and sometimes inter-stage impedances that balance performance, robustness, and manufacturability. This decision cannot be made at the schematic level alone—it requires system awareness and physical intuition.

This is where RF projects often encounter hidden risk. Many designs optimize for gain or noise in isolation, unintentionally pushing the circuit closer to instability, compression, or sensitivity to process and layout variation. These issues may not surface until first silicon, OTA testing, or field deployment—when fixes become expensive and schedules slip.

ORTENGA’s RF audit approach is designed to uncover these risks early. Rather than reviewing schematics in isolation, ORTENGA analyzes RF circuits through the lens of impedance trade spaces—examining how matching choices interact with device physics, bias conditions, layout parasitics, and system-level requirements. The goal is not to redesign blindly, but to expose where impedance decisions constrain or endanger system performance.

By auditing LNAs, PAs, and inter-stage networks at the impedance level, ORTENGA helps teams understand why a design behaves the way it does—and what tradeoffs must change to achieve predictable results. The outcome is clearer root cause identification, fewer design spins, and RF systems that perform as expected outside the simulator.

In RF, success is not determined by how clean the schematic looks. It is determined by whether impedance choices were made deliberately, with full awareness of their consequences.

Call to Action — RF Design Audit

Many RF issues are not caused by missing components or incorrect schematics—they stem from unexamined impedance decisions made early in the design.

ORTENGA’s RF Audit service helps teams identify where impedance tradeoffs quietly limit noise performance, gain margin, output power, or stability—before those issues surface in silicon, OTA testing, or the field.

Through a system-level, impedance-driven review of LNAs, PAs, and inter-stage networks, ORTENGA:

• Exposes hidden stability and robustness risks
• Identifies mismatches between simulation assumptions and physical behavior
• Clarifies which impedance tradeoffs matter—and which do not
• Reduces unnecessary design spins, cost overruns, and schedule delays

If your RF design is underperforming, difficult to debug, or approaching a critical milestone, an impedance-focused audit can reveal what schematics alone cannot.

👉 Partner with ORTENGA to audit your RF design at the level where real performance is decided.

 

Managing Post-Tapeout Risk: The Role of FIB in ASIC Programs

ASIC design and development progress through multiple design reviews—from early architecture through final tapeout. One of the most critical checkpoints is schematic-versus-layout (SVS) verification, where any discrepancy must be identified and resolved before masks are released.

Despite rigorous flows, miscommunication, integration gaps, or simple oversights can still occur.

These post-tapeout issues generally fall into two categories:

• Functionality issues – The circuit does not operate at all. These failures prevent any meaningful evaluation or characterization.
• Performance issues – The circuit functions correctly but fails to meet one or more performance metrics (e.g., gain, noise, speed, power).

Functionality issues are the most severe. Given ASIC tapeout costs and the long turnaround time for a full re-spin, alternative debug paths become critical.

Focused Ion Beam (FIB) as a Debug and Recovery Tool

Focused Ion Beam (FIB) techniques enable localized, post-silicon modifications—primarily at the top metal layers—to support debugging, validation, and limited functional recovery.

Typical FIB use cases include:

• Metal layer cuts or reconnects
• Signal rerouting for debug visibility
• Temporary fixes to validate hypotheses before re-tapeout

While FIB is not a substitute for proper design closure, it can significantly reduce risk, cost, and schedule impact when unexpected functional issues surface.

Where ORTENGA Fits

ORTENGA works with teams before and after tapeout to reduce execution risk across complex silicon programs.

We help clients:

• Identify which technical features truly map to business goals
• Distinguish between recoverable post-silicon issues and full re-spin conditions
• Align Antenna, ASIC, HW, FW, and SW decisions at the system level

Our engineering network brings hands-on experience from Autonomous Automotive, SATCOM, radar, Smart City, Wi-Fi, and mobile terrestrial radio systems, enabling faster root-cause isolation and more informed recovery paths.

Partner with ORTENGA across product concept, design, and development to ensure technical decisions remain aligned with the outcomes your business depends on.

Before committing to a re-spin, get clarity.
ORTENGA provides independent, system-level insight across Antenna, ASIC, HW, FW, and SW—helping teams avoid unnecessary cost, reduce schedule risk, and make technically sound go/no-go decisions.

AI Doesn’t Need More Compute—It Needs Less Data Movement

Why Processing-in-Memory Is the Next Breakthrough in AI ASIC Architecture

As AI models scale, power consumption is no longer dominated by computation—it is dominated by the cost of moving data between memory and compute.

Modern AI workloads process massive volumes of data, repeatedly and at scale. To keep up, AI systems rely on high-speed interconnects and SERDES links operating at tens to hundreds of gigasamples per second. While these links solve bandwidth, they do so at a steep power cost.

The industry response has largely been to add more compute, faster interconnects, and wider memory buses. Yet power efficiency continues to degrade.

This is not a technology failure.
It is an architecture failure.

Legacy Architecture Was Not Wrong

Legacy processor architectures were built around a product concept that made sense for decades:

• Separate data storage from computation
• Move data to compute when needed
• Optimize cost, manufacturability, and generality

For CPUs, GPUs, and traditional accelerators, this separation was cost-effective and power-efficient. The architecture matched the problem.

That architecture was not wrong.

The failure occurred later—when the same product concept was reused for AI systems without being audited.

The Real Failure: Bottom-Up Reuse Without Audit

AI workloads introduced fundamentally different constraints:

• Massive, repeated data movement
• Power dominated by memory access, not arithmetic
• Scaling behavior driven by data locality
• Efficiency limited by distance, not FLOPS

Yet many early AI ASICs were designed bottom-up:
starting from familiar processor and memory blocks, adapting incrementally, and assuming the system would converge.

Assumptions were inherited instead of verified.
Architecture was chosen before requirements were defined.

No one stopped to ask whether processor–memory separation still made sense for AI.

This is not innovation—it is architectural inertia.

Top-Down Design Changes the Outcome

Top-down system design starts from a different place:

• Define AI use cases first
• Audit assumptions explicitly
• Derive constraints from workloads
• Select architecture last

When AI is framed correctly—as a data-movement-dominated system—the technical implications become unavoidable:

Moving data costs more energy than computing on it.

Once this is acknowledged, the architecture must change.

Processing-in-Memory Is the Result of Doing the Audit Correctly

Processing-in-Memory (PIM) is not a clever optimization or a late-stage enhancement.

It is the natural outcome of decomposing the AI product concept into correct system requirements.

By moving compute closer to—or directly inside—memory:

• Data movement is reduced
• SERDES dependency is lowered
• Power efficiency improves structurally, not marginally

PIM is not new thinking.
It is disciplined thinking applied correctly.

Why Audit → Design → Validate Matters

The pattern that led to inefficient AI ASICs is common across many complex systems:

• Bottom-up design
• Unverified assumptions
• Architecture locked too early
• Requirements back-filled to justify decisions

The antidote is a disciplined, top-down process.

Audit → Design → Validate Applied to AI

Audit

• Define AI use cases explicitly
• Challenge legacy processor assumptions
• Identify data movement as the dominant constraint

Design

• Derive architecture from constraints
• Place compute where data resides
• Co-design memory and processing

Validate

• Measure end-to-end system power
• Validate assumptions with real workloads
• Confirm scaling behavior before silicon is frozen

Skipping any of these steps leads to systems that work—but scale poorly.

Final Thought

Efficient AI architectures do not emerge from reusing familiar blocks.
They emerge from auditing the right product concept.

Processing-in-Memory is not the future because it is fashionable.
It is the future because it is architecturally correct for AI.

ORTENGA helps teams audit assumptions, design intentionally, and validate system-level trade-offs before capital and silicon are committed.

If you are defining a new AI ASIC—or questioning the efficiency of an existing one—the most important decision is not how much compute to add.

It is whether your architecture was ever audited for the problem it is trying to solve.

Risk discovered early is manageable.
Risk discovered late destroys ROI.

ORTENGA — Audit. Design. Validate.

 

Choosing the Wrong AI Processor Is an Expensive Mistake

Why Architecture Decisions Must Precede ASIC Design

Most AI ASIC programs miss their power targets, slip their schedules, and burn capital—not because the math is wrong, but because the processor architecture was chosen before the product constraints were understood.

The figure above shows why processor selection is not a compute preference, but a product decision—where cost, power, and schedule risk are locked in long before ASIC design begins.

AI Processors: Compute Is Easy, Constraints Are Not

An Artificial Intelligence (AI) processor’s fundamental role is to perform large-scale numerical computation—commonly expressed as:

D = A × B + C

In practice, this computation spans high-dimensional matrices and tensors across massive parallel hardware. While the math is universal, the way it is executed in silicon is not. Power limits, memory bandwidth, data movement, and algorithm stability ultimately determine whether an AI processor succeeds as part of a product—or fails as an expensive science project.

To address different AI workloads, several processor architectures have emerged:

• GPU (Graphics Processing Unit)
• TPU (Tensor Processing Unit)
• EPU (Edge Processing Unit)
• NPU and other domain-specific accelerators

Each architecture optimizes a different trade space. Problems arise when teams select one before auditing product constraints and system assumptions.

GPU: Flexible Compute, Expensive at Scale

GPUs are often the default choice for AI teams because they offer flexibility and fast time-to-first-demo. That flexibility, however, comes at a cost.

GPUs are designed for broad, general-purpose parallel workloads—not tightly constrained products. As a result, they frequently suffer from inefficient silicon utilization, higher power consumption, and inflated bill of materials when deployed at scale. For inference-heavy or fixed-function workloads, GPUs often deliver performance that the product neither needs nor can afford.

What begins as a convenient development choice can quietly become a long-term cost, power, and thermal liability.

TPU: Maximum Throughput, Minimum Tolerance for Change

TPUs shine when algorithms, tensor dimensions, and data flow are well understood and stable. Their strength—exceptional efficiency for dense tensor operations—is also their risk.

Once a TPU architecture is committed, changes propagate across memory hierarchy, data movement, and compute pipelines. Late algorithm updates or model evolution can trigger significant non-recurring engineering (NRE) costs and schedule slips.

Without an upfront architecture audit, teams often discover too late that a TPU optimized for peak throughput lacks the flexibility their product roadmap actually requires.

EPU: Power-Limited, Product-Defined

Edge Processing Units are shaped by real-world product constraints: battery life, thermal dissipation, latency, and user experience. Unlike GPUs or TPUs, EPUs cannot compensate for architectural inefficiency with more power or memory bandwidth.

Every assumption—model complexity, precision, tensor order, and data movement—must be correct early. When those assumptions are wrong, products miss performance targets or violate power budgets. At that point, fixes are costly, slow, or impossible once silicon is frozen.

For edge products, architecture errors are not incremental—they are existential.

Why AI ASICs Fail Before Design Begins

At the ASIC level, AI performance and efficiency are driven less by raw compute and more by system-level decisions:

• Tensor dimensionality and execution order
• On-chip interconnect and bus bandwidth
• Memory architecture and access patterns
• High-Bandwidth Memory (HBM) integration
• Compute-to-memory balance

When architecture decisions are made without a disciplined audit of these factors, teams lock in risk that software cannot later undo.

Architecture Is the First Irreversible Decision

Choosing the wrong AI processor is not a software mistake—it is an architectural commitment with permanent cost, power, and schedule consequences.

This is why architecture selection must occur before ASIC design, not during it.

Before committing to an AI ASIC Statement of Work, ORTENGA audits your AI workload, product constraints, and system assumptions to determine whether GPU-class flexibility, TPU-class throughput, or EPU-class efficiency truly aligns with your product.

By defining the right architecture before silicon design begins, ORTENGA helps you avoid re-spins, protect return on investment, and deliver AI performance that fits the product—not the hype.

Partner with ORTENGA to audit, specify, and de-risk your AI ASIC architecture before capital is committed.

 

Wafer Maps Don’t Lie: How Yield Decisions Are Really Made

From Wafer Probe Data to Cost and Margin Outcomes

Wafer probe doesn’t just tell you which dies passed or failed—it quietly determines yield, cost, and margin long before packaging begins, if you know how to read it.

Wafer Probe, Binning, and Wafer Maps

Semiconductor wafers go through a long, complex, and expensive manufacturing cycle before fabrication is complete. The turnaround time for a wafer lot typically ranges from 30 to 60 days, depending on process technology and the foundry.

Once fabrication is finished, wafers enter wafer probe, where the electrical behavior of every individual die is measured for the first time. This step provides the earliest visibility into how the silicon actually behaves, not how it was expected to behave.

Wafer probing is performed using Automatic Test Equipment (ATE)—robotic systems capable of executing thousands of test vectors across every die. A single wafer may contain thousands of ASIC dies, each tested individually.

Binning: Organizing Silicon Reality

Each die is assigned a bin number based on its test results:

• Bin 1: Dies that pass all functional and parametric tests
• Other bins: Dies that fail specific criteria
  • Some fail a single marginal parameter
  • Others fail fundamental conditions such as excessive current draw

Each bin represents a distinct failure mode, not simply “good” versus “bad.”

Wafer Maps: The Missing Context

The results of wafer probing are stored electronically as a wafer map—a spatial representation of bin distribution across the wafer.

Wafer maps reveal:

• Systematic versus random failures
• Edge-related, center-related, or layout-correlated effects
• Process drift and design margin weaknesses

This information is passed downstream to guide dicing, sorting, packaging, and yield analysis. However, its real value lies earlier—in how decisions are made once the data is available.

The Post-Silicon Yield Decision Loop

Once silicon exists, success is no longer driven by design intent alone. It is driven by decisions made under schedule, cost, and uncertainty constraints.

Measure → Interpret → Decide

This is the framework that governs real yield outcomes.

Measure: What the Silicon Tells You

Measurement captures the objective behavior of the silicon:

• Wafer probe results
• Parametric limits and margins
• Bin classifications per die
• Full-wafer spatial data

Silicon does not speculate or explain—it reports exactly how it behaves.

Silicon tells the truth—but without context.

Early Silicon Access: Speed Before Perfection

In early design validation for commercial products, time-to-market is often the dominant metric. In these programs, even a few days of delay can materially impact competitiveness, revenue, or customer commitments.

To accelerate learning, teams may intentionally include a subset of dies that are “blind built” or only partially screened. These dies are not intended to represent production yield.

They are used to:

• Enable early engineering access to new silicon
• Validate architectural assumptions
• Bring up firmware, software, and system integration
• Identify catastrophic or systemic design issues as early as possible

In this context, a blind die is not a defect—it is a deliberate engineering strategy.

The tradeoff is explicit:

• Faster insight in exchange for incomplete test coverage
• Directional learning before full test collateral matures

This approach is common in commercial programs where schedule risk outweighs short-term yield optimization.

Speed is a decision—not an accident.

Interpret: Turning Data Into Insight

Interpretation converts raw measurements into understanding:

• Wafer maps and heat maps
• Spatial clustering analysis
• Correlation to layout, process, and power distribution
• Separation of design limits from process variation

Blind-die data must be interpreted carefully. It provides early signal, not yield truth.

This step distinguishes:

• Recoverable yield loss
• Structural design limitations
• Test coverage gaps versus real silicon behavior

Patterns reveal root causes.

Decide: Where Economics Are Set

Decisions determine whether yield becomes a cost problem—or a competitive advantage:

• Bin reclassification strategies
• Yield versus performance tradeoffs
• Process tuning versus redesign
• Scrap, rework, hold, or ship decisions

Every decision made here compounds across volume and time.

Decisions set economics.

Dicing, Sorting, and Yield Economics

After wafer probe, wafers are diced and dies are physically sorted by bin:

• Bin 1 dies proceed to packaging
• Other bins are analyzed for recovery, reuse, or root cause

Yield directly determines cost per die. Small improvements at wafer probe scale into significant margin impact in production.

Yield is not a manufacturing outcome—it is a decision outcome.

Teams that measure accurately, interpret correctly, and decide deliberately protect margin and schedule. Teams that don’t pay for it later.

ORTENGA helps companies operate after wafer probe and before costs harden, translating wafer-level data into informed decisions across ASIC, antenna, algorithms, hardware, firmware, and software domains.

We don’t just read wafer maps.
We help leadership decide what to do next.