Split Semiconductor Wafers

ASIC is fundamental of many high-volume engineering solutions for commercial products.

Any product is either part of a larger system or it is actually a system.

All systems or even subsystems are comprised HW, FW, and SW.

The overall system performance is dependent on these components, HW, FW, and SW.

For a laboratory prototype device to be called an actual commercial product, it has to not only be functional but also meet specifications/system requirements over part-to-part aka process, voltage, temperature wide variations, better known as P.V.T. in the semiconductor industry.

A device that cannot handle cold or hot temperature is just a prototype, or proof of concept, and would not see commercialization daylight to return the investment.

To become commercial product, any device must be functional and meeting performance over P.V.T.

Split semiconductor wafers are intentionally altered during the engineering semiconductor fabrications in a such way that they mimic chemical variations which are typical for ASIC-to-ASIC variations of semiconductor fabrications during production phase.

The split semiconductor wafers are typically designed for at least 3 production speed variations, Slow, Nominal, and Fast.

The speed is associated with gate or transistor electron conductions performance.

Regarding RFIC, the semiconductor speed impacts gain which in turn the noise figure and non-linearity in the receiver chain.  The speed impacts output power and non-linearity in the transmitter chain.

Regarding SoC, the semiconductor speed impacts the switching speed which in turn the data throughput handling of the SoC.

ORTENGA helps businesses to identify required technical features to realize their business goals.

Partner ORTENGA in your next product concept, design, and development to realize that business goal.

ORTENGA has seasoned engineering from ASIC, SATCOM, radar, and mobile terrestrial radio communications industries in HW, FW, and SW engineering disciplines.

 

What are Pilot Test Chips and Pizza Masks? 

Application Specific Integrated Circuits, aka ASIC, are high volume electronic circuits which provide functionality of some portion of communications and/or radar systems. One of major cost components of these ASIC, is semiconductor mask.  Semiconductor masks are used for lithographically fabricating the semiconductor devices onto wafer.  Each wafer requires multiple masks for various layers of fabrications and etching. A typical vanilla CMOS process could easily have 200 masks or more and they could easily cost as much ~$3M depending on the geometry and size of the gates.

Each all layer revisions of ASIC require all ~200 masks; therefore it becomes prohibitively expensive for smaller companies or even big corporations to tape out any design for single project/product.

In order to save cost for any trial of ASIC before design is finalized, it is customary to run some pilot test chips to validate the design as well as the process performances.  For test chips run, it should only be enough number of them to be validated and characterized for desired performances, KPI.

Therefore, many semiconductor fabrications offer Pizza Mask, where number of companies can share the cost for the masks, ~$3M, and get only small portion of wafer area, “pizza”.  Very large corporations typically have their own pizza masks for multiple internal projects, test chips.  Or tandem with another project masks for couple hundred devices.

Each wafer lot is typically 25 wafers, and small portion of pizza/wafer, can produce few hundred devices per lot, enough to validate design topology and performance metrics.

Augment ORTENGA in your semiconductor device design and developments to utilize cost saving proven techniques which are not only benefits R&D cost, but also improves TTM, hence ROI.

 

Device Technology Push for mmW Bands 

CMOS technology has been the technology of choice for baseband digital and mixed signaling for number of decades.  In that past decade, CMOS was utilized for some of RF transceivers.

As radio transceivers go into mmW bands, the use of CMOS for RF signaling becomes limited and III-V compound technology are required to meet the specifications.  The following chart illustrates the Maximum Stable Gain, MSG comparison for CMOS vs. III-V compound technologies over the next few years.

ORTENGA has seasoned engineering from ASIC, SATCOM, radar, and mobile terrestrial radio communications industries in HW, FW, and SW engineering disciplines.