Split Semiconductor Wafers

ASIC is fundamental of many high-volume engineering solutions for commercial products.

Any product is either part of a larger system or it is actually a system.

All systems or even subsystems are comprised HW, FW, and SW.

The overall system performance is dependent on these components, HW, FW, and SW.

For a laboratory prototype device to be called an actual commercial product, it has to not only be functional but also meet specifications/system requirements over part-to-part aka process, voltage, temperature wide variations, better known as P.V.T. in the semiconductor industry.

A device that cannot handle cold or hot temperature is just a prototype, or proof of concept, and would not see commercialization daylight to return the investment.

To become commercial product, any device must be functional and meeting performance over P.V.T.

Split semiconductor wafers are intentionally altered during the engineering semiconductor fabrications in a such way that they mimic chemical variations which are typical for ASIC-to-ASIC variations of semiconductor fabrications during production phase.

The split semiconductor wafers are typically designed for at least 3 production speed variations, Slow, Nominal, and Fast.

The speed is associated with gate or transistor electron conductions performance.

Regarding RFIC, the semiconductor speed impacts gain which in turn the noise figure and non-linearity in the receiver chain.  The speed impacts output power and non-linearity in the transmitter chain.

Regarding SoC, the semiconductor speed impacts the switching speed which in turn the data throughput handling of the SoC.

ORTENGA helps businesses to identify required technical features to realize their business goals.

Partner ORTENGA in your next product concept, design, and development to realize that business goal.

ORTENGA has seasoned engineering from Autonomous Automotive, SATCOM, radar, Smart City, and Mobile Terrestrial Radio Communications System industries in ASIC, HW, FW, and SW engineering disciplines.

 

What are Pilot Test Chips and Pizza Masks? 

Application Specific Integrated Circuits, aka ASIC, are high volume electronic circuits which provide functionality of some portion of communications and/or radar systems. One of major cost components of these ASIC, is semiconductor mask.  Semiconductor masks are used for lithographically fabricating the semiconductor devices onto wafer.  Each wafer requires multiple masks for various layers of fabrications and etching. A typical vanilla CMOS process could easily have 200 masks or more and they could easily cost as much ~$3M depending on the geometry and size of the gates.

Each all layer revisions of ASIC require all ~200 masks; therefore it becomes prohibitively expensive for smaller companies or even big corporations to tape out any design for single project/product.

In order to save cost for any trial of ASIC before design is finalized, it is customary to run some pilot test chips to validate the design as well as the process performances.  For test chips run, it should only be enough number of them to be validated and characterized for desired performances, KPI.

Therefore, many semiconductor fabrications offer Pizza Mask, where number of companies can share the cost for the masks, ~$3M, and get only small portion of wafer area, “pizza”.  Very large corporations typically have their own pizza masks for multiple internal projects, test chips.  Or tandem with another project masks for couple hundred devices.

Each wafer lot is typically 25 wafers, and small portion of pizza/wafer, can produce few hundred devices per lot, enough to validate design topology and performance metrics.

Augment ORTENGA in your semiconductor device design and developments to utilize cost saving proven techniques which are not only benefits R&D cost, but also improves TTM, hence ROI.

 

Device Technology Push for mmW Bands 

CMOS technology has been the technology of choice for baseband digital and mixed signaling for number of decades.  In that past decade, CMOS was utilized for some of RF transceivers.

As radio transceivers go into mmW bands, the use of CMOS for RF signaling becomes limited and III-V compound technology are required to meet the specifications.  The following chart illustrates the Maximum Stable Gain, MSG comparison for CMOS vs. III-V compound technologies over the next few years.

ORTENGA has seasoned engineering from Autonomous Automotive, SATCOM, radar, Smart City, and Mobile Terrestrial Radio Communications System industries in ASIC, HW, FW, and SW engineering disciplines.

 

Transistor Semiconductor Process Selection fT, fu, fmax

fT, Transition frequency is the transistor highest frequency where the current gain is unity or 0 dB, beyond this frequency there is no current gain.

fmax, maximum frequency is the transistor highest frequency where the unilateral gain becomes unity or 0 dB, beyond this frequency there is no power gain.

Many useful circuits require either current, voltage, or power gain.

As the application of radio frequencies increases, the required transistor’s fT increases too.

For given semiconductor process, the gain slop is negative with 6dB/Octave or 20dB/decade in frequency.

Silicon processes’ fT is a technical driver and depending on required “gain” or applicability a process is down-selected.

Obviously, cost is another driver for down-selecting the semiconductor process.

The cost of wafer drives the cost of ASIC.

The cost of wafer depends on the size of the wafer, the semiconductor process, and the number of lithography masks, which together drive the die per wafer cost.

As the wafer size increases, the number of dies per wafer increase, therefore ASIC cost decreases.

The silicon wafers, CMOS process in particular could be as large 15” diameter nowadays.

Higher radio frequencies’ circuitry requires III-V compound semiconductor process with higher fT, such as GaAs, GaN, InP, etc.

The III-V wafers could be as large as 8” diameter nowadays and they are fewer fabs that can develop them.

The III-V compound semiconductors are typically used for applications with high RF performance which are less cost sensitive, such as; advance radio, radar, space, or specialized and custom-made radio front ends.

Furthermore, ASIC cost depends on wafer yield, wafer probe test time, packaged ASIC test time, and the package itself which could be significant portion of the total cost.

The wafer yield impacts the cost of ASIC and depends on circuit design topology and implementations as well as selected process tolerances.

Partner ORTENGA to succeed in your design and product delivery to the market.

ORTENGA has seasoned engineering from Autonomous Automotive, SATCOM, radar, Smart City, WiFi, and Mobile Terrestrial Radio Communications System industries in Antenna, ASIC, Algorithm, HW, FW, and SW engineering disciplines.

 

ASIC FIB

ASIC design and development go through multiple design reviews from early stage until tapeout.

During tapeout schematic vs. layout should be compared and any discrepancy should be carefully resolved.

Still, there are miscommunications and simple overlook occur.

These errors cause functionality at most and sometime performance issues only.

Functionality issues are the one where the circuit does not function at all.

Whereas performance issues are the one where the circuit functions yet do not meet all some performance metrics.

Functionality issues prevent any evaluation of the circuit.

Given ASIC tapeout expenses and timeline to fix any functional issue, there could be alternative option, FIB.

Focused Ion Beam, FIB allows to alter some changes to top layer of silicon for debugging and testing.

The easiest changes are to the metal layer connectivity.

ORTENGA helps businesses to identify required technical features to realize their business goals.

Partner ORTENGA in your next product concept, design, and development to realize that business goal.

ORTENGA has seasoned engineering from Autonomous Automotive, SATCOM, radar, Smart City, WiFi, and Mobile Terrestrial Radio Communications industries in Antenna, ASIC, HW, FW, and SW engineering disciplines.

 

Wafer Probe, Binning, and Wafer Map

Semiconductor wafers go through a long and costly expenses to be developed during production phase of any wafer lot.

The turn-around time is typically anywhere between 30 to 60 days depending on the process and fab house.

After the completion of the wafer lot, they go through wafer probe for design and process validations.

This testing occurs with Automatic Test Equipment, ATE which are similar to robot with testing capabilities.

Each wafer has thousands of Dies, i.e. ASIC, which would be tested individually.

A good die would pass all expected wafer test, Bin 1.

On the other hand, the bad dies are binned for various failures.

For instance, a die may fail for merely parametric of a single parameter marginally, Bin 2, while another die fails simple drawing current, Bin 99.

An electronic record of these failures with various bin numbers will be saved and called Wafer Map and will be passed on to the next step.

The next step is wafer dice and sort each bin number separately.

Obviously, Bin 1 Dies will be used for packaging.

Other Bins have to be analyzed if improving yield or root cause analysis is desired.

The yield impacts the cost of die per wafer.

ORTENGA has seasoned engineering from Autonomous Automotive, SATCOM, radar, Smart City, WiFi, and Mobile Terrestrial Radio Communications System industries in Antenna, ASIC, Algorithm, HW, FW, and SW engineering disciplines.

 

Delta Sigma Modulator, DSM

Ultra wide bandwidth data converters, ADC and DAC are becoming required for many applications, such as; advanced radio communications and radar systems.

UWB data converters enable monitoring/generating multiple signals within the overall system whether that is radio communications or radar applications.

In radio communications, the faster response time translate to shorter processing time for multiple signals.

In radar, the faster response time translate to shorter time to be aware of multiple targets.

DSM architecture can be configured for high resolution and low noise for UWB applications.

ORTENGA works with client and stakeholders to identify goals and deliverables of the project.

ORTENGA helps businesses to identify required technical features to realize their business goals.

Partner ORTENGA in your next product concept, design, and development to realize that business goal.

ORTENGA has seasoned engineering from Autonomous Automotive, SATCOM, radar, Smart City, WiFi, and Mobile Terrestrial Radio Communications System industries in Antenna, ASIC, Algorithm, HW, FW, and SW engineering disciplines.