Semiconductor Geometry, Moor’s Law Applicability

 

Digital circuitry relies on switching transistors, binary logic, 0 and 1.

Switching technology is directly proportional to semiconductor geometry.

Therefore, by reducing the geometry, the switching technology shrinks.

The size reductions have two impacts, the cost by increasing die per wafer, as well as reducing sleep current/power consumption.

Waveform generation and waveform analysis occur in digital circuits.

DSP is implemented by digital circuits with FPGA or equivalent processor.

The actual information is embedded in the digital waveform.

Analog circuitry, in particular, RF circuits are comprised of capacitors, inductors, as well as amplifiers.

It is only the amplifiers which utilize transistors and are relatively few comparing to digital circuits.

The inductance and capacitance values depend on semiconductor/silicon area and relative dielectric and permeability constants therefore their size does not scale with semiconductor geometry.

In reality the RF circuits scale with wavelength (frequency), therefore at operational frequencies the RF circuitry is small portion of the overall system, i.e., Digital, Mixed Signal, Analog circuits.

It is only signal conditioning and integrity of EM waves (carrier) which occur in the RF circuits.

ORTENGA helps businesses to identify required technical features to realize their business goals.

ORTENGA provides structured engineering leadership across antenna architecture, realization planning, integration, and deployment validation to reduce downstream realization risk and improve alignment between engineering execution and business objectives.

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AI Processor

Artificial Intelligence, AI processor function is to compute D = A x B + C with multiple dimensions matrix manipulations.

Typically, AI utilizes either Graphical Processor Unit, GPU, Neural Processor Unit, NPU, or Edge Processor Unit, EPU, or Tensor Processor Unit, TPU.

EPU is used for Edge device, such as Smart Phone that is power limited yet needs some AI capability, e.g. voice or image recognition.

TPU is used for high level of computations for multivariable input data or features, e.g. image processing.

Each processor is tailored for certain AI algorithm and its power consumption either within FPGA or AI ASIC.

Multi variable matrix, Tensor, manipulation order of computation, BUS speed, and High Bandwidth Memory, HBM are main drivers of ASIC accelerator design.

ORTENGA provides structured engineering leadership across antenna architecture, realization planning, integration, and deployment validation to reduce downstream realization risk and improve alignment between engineering execution and business objectives.

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ARM Processor

Advanced RISC Machine, ARM processor is an advanced Reduced Instruction Set Computer, RISC.

RISC is designed for faster instructions execution, i.e. execution in HW as opposed to SW.

In addition, RISC is designed for lower power consumption, i.e. executing instruction per cycle.

The above two features are desired for Edge, Mobile, or battery-operated devices.

ORTENGA provides structured engineering leadership across antenna architecture, realization planning, integration, and deployment validation to reduce downstream realization risk and improve alignment between engineering execution and business objectives.

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AI Edge Processor

Artificial Intelligence, AI Edge relies on ARM processor architecture.

ARM processor architecture is known for its speed and low power consumption.

AI Edge processor requires even faster and lower power consumption compare to its ARM predecessors.

That implies faster and larger or deeper internal registers and Cache.

In addition, the AI Edge processor is required to consume lower power per instruction in comparison to its ARM predecessors.

If the required speed is more than what the semiconductor process can achieve, then multi-core processor is utilized to work in parallel and achieve higher throughput per instruction.

ORTENGA provides structured engineering leadership across antenna architecture, realization planning, integration, and deployment validation to reduce downstream realization risk and improve alignment between engineering execution and business objectives.

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AI Neural Processor ASIC Requirements

Neural processor is a simple processor that performs single computation, e.g., addition, multiplication, etc.

Consequently, to execute a simple algorithm, thousands of neurons are required.

Therefore, to execute a tensor with large dimensions, millions of neurons are required.

As a result, the power consumption would become a limiting factor for real world problems, unless the following neuron behavior can be designed and met:

  1. Zero power consumption for sleeping/unused neurons
  2. Low amount of power for working neurons
  3. Low complexity or low number of operations algorithms are designed and utilized

ORTENGA provides structured engineering leadership across antenna architecture, realization planning, integration, and deployment validation to reduce downstream realization risk and improve alignment between engineering execution and business objectives.

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Choosing the Wrong AI Processor Is an Expensive Mistake

Why Architecture Decisions Must Precede ASIC Design

Most AI ASIC programs miss their power targets, slip their schedules, and burn capital—not because the math is wrong, but because the processor architecture was chosen before the product constraints were understood.

The figure above shows why processor selection is not a compute preference, but a product decision—where cost, power, and schedule risk are locked in long before ASIC design begins.

AI Processors: Compute Is Easy, Constraints Are Not

An Artificial Intelligence (AI) processor’s fundamental role is to perform large-scale numerical computation—commonly expressed as:

D = A × B + C

In practice, this computation spans high-dimensional matrices and tensors across massive parallel hardware. While the math is universal, the way it is executed in silicon is not. Power limits, memory bandwidth, data movement, and algorithm stability ultimately determine whether an AI processor succeeds as part of a product—or fails as an expensive science project.

To address different AI workloads, several processor architectures have emerged:

  • GPU (Graphics Processing Unit)
  • TPU (Tensor Processing Unit)
  • EPU (Edge Processing Unit)
  • NPU and other domain-specific accelerators

Each architecture optimizes a different trade space. Problems arise when teams select one before auditing product constraints and system assumptions.

GPU: Flexible Compute, Expensive at Scale

GPUs are often the default choice for AI teams because they offer flexibility and fast time-to-first-demo. That flexibility, however, comes at a cost.

GPUs are designed for broad, general-purpose parallel workloads—not tightly constrained products. As a result, they frequently suffer from inefficient silicon utilization, higher power consumption, and inflated bill of materials when deployed at scale. For inference-heavy or fixed-function workloads, GPUs often deliver performance that the product neither needs nor can afford.

What begins as a convenient development choice can quietly become a long-term cost, power, and thermal liability.

TPU: Maximum Throughput, Minimum Tolerance for Change

TPUs shine when algorithms, tensor dimensions, and data flow are well understood and stable. Their strength—exceptional efficiency for dense tensor operations—is also their risk.

Once a TPU architecture is committed, changes propagate across memory hierarchy, data movement, and compute pipelines. Late algorithm updates or model evolution can trigger significant non-recurring engineering (NRE) costs and schedule slips.

Without an upfront architecture audit, teams often discover too late that a TPU optimized for peak throughput lacks the flexibility their product roadmap actually requires.

EPU: Power-Limited, Product-Defined

Edge Processing Units are shaped by real-world product constraints: battery life, thermal dissipation, latency, and user experience. Unlike GPUs or TPUs, EPUs cannot compensate for architectural inefficiency with more power or memory bandwidth.

Every assumption—model complexity, precision, tensor order, and data movement—must be correct early. When those assumptions are wrong, products miss performance targets or violate power budgets. At that point, fixes are costly, slow, or impossible once silicon is frozen.

For edge products, architecture errors are not incremental—they are existential.

Why AI ASICs Fail Before Design Begins

At the ASIC level, AI performance and efficiency are driven less by raw compute and more by system-level decisions:

  • Tensor dimensionality and execution order
  • On-chip interconnect and bus bandwidth
  • Memory architecture and access patterns
  • High-Bandwidth Memory (HBM) integration
  • Compute-to-memory balance

When architecture decisions are made without a disciplined audit of these factors, teams lock in risk that software cannot later undo.

Architecture Is the First Irreversible Decision

Choosing the wrong AI processor is not a software mistake—it is an architectural commitment with permanent cost, power, and schedule consequences.

This is why architecture selection must occur before ASIC design, not during it.

Before committing to an AI ASIC Statement of Work, ORTENGA audits your AI workload, product constraints, and system assumptions to determine whether GPU-class flexibility, TPU-class throughput, or EPU-class efficiency truly aligns with your product.

By defining the right architecture before silicon design begins, ORTENGA helps you avoid re-spins, protect return on investment, and deliver AI performance that fits the product—not the hype.

ORTENGA provides structured engineering leadership across antenna architecture, realization planning, integration, and deployment validation to reduce downstream realization risk and improve alignment between engineering execution and business objectives.

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