Transistor Semiconductor Process Selection fT, fu, fmax

fT, Transition frequency is the transistor highest frequency where the current gain is unity or 0 dB, beyond this frequency there is no current gain.

fmax, maximum frequency is the transistor highest frequency where the unilateral gain becomes unity or 0 dB, beyond this frequency there is no power gain.

Many useful circuits require either current, voltage, or power gain.

As the application of radio frequencies increases, the required transistor’s fT increases too.

For given semiconductor process, the gain slop is negative with 6dB/Octave or 20dB/decade in frequency.

Silicon processes’ fT is a technical driver and depending on required “gain” or applicability a process is down-selected.

Obviously, cost is another driver for down-selecting the semiconductor process.

The cost of wafer drives the cost of ASIC.

The cost of wafer depends on the size of the wafer, the semiconductor process, and the number of lithography masks, which together drive the die per wafer cost.

As the wafer size increases, the number of dies per wafer increase, therefore ASIC cost decreases.

The silicon wafers, CMOS process in particular could be as large 15” diameter nowadays.

Higher radio frequencies’ circuitry requires III-V compound semiconductor process with higher fT, such as GaAs, GaN, InP, etc.

The III-V wafers could be as large as 8” diameter nowadays and they are fewer fabs that can develop them.

The III-V compound semiconductors are typically used for applications with high RF performance which are less cost sensitive, such as; advance radio, radar, space, or specialized and custom-made radio front ends.

Furthermore, ASIC cost depends on wafer yield, wafer probe test time, packaged ASIC test time, and the package itself which could be significant portion of the total cost.

The wafer yield impacts the cost of ASIC and depends on circuit design topology and implementations as well as selected process tolerances.

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Device Technology Push for mmW Bands 

CMOS technology has been the technology of choice for baseband digital and mixed signaling for number of decades.  In that past decade, CMOS was utilized for some of RF transceivers.

As radio transceivers go into mmW bands, the use of CMOS for RF signaling becomes limited and III-V compound technology are required to meet the specifications.  The following chart illustrates the Maximum Stable Gain, MSG comparison for CMOS vs. III-V compound technologies over the next few years.

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RF Amplifiers

RF amplifiers are used both in radio transmitter and receiver chains.

In the transmitter, there are two amplifiers, Drive Amplifier, DA and Power Amplifier, PA.

DA is typically post transceiver yet before PA, hence Drive Amplifier.

PA is the last amplification stage before the signal is delivered to antenna.

The objectives of both DA and PA are to amplify and increase the signal to adequate level before transmission into the air.

In the receiver chain, there are also at least two stages of amplifications.

Low Noise Amplifier, LNA is the closed amplifier to the antenna.  It is function is to amplify the small incoming signal yet at add very small amount of thermal noise.

It is less known to many that every electronic circuit add some noise to the signal and reduces SNR.  That applies to amplifiers too.

Trans-Impedance Amplifier, TIA is another amplifier typically after the frequency conversion and before ADC.  TIA could be known as IF amplifier.

Regardless of amplifier function, they are typically comprised of transistors active device for providing gain as well as input and output matching network.

What differentiate all of the above amplifiers, are two things.

First the transistor selected for gain or amplification.

Second the input and output matching network objective.

While the name may suggest the matching network job is to match the impedance.

The reality is different.

The matching network for LNA is noise match, while for PA is to power match.

In both cases the matching network is supposed to their job while keeping the circuit stable.

The stability is unspoken constraints yet implied and perhaps the most important requirement for any amplifier is to amplify not oscillate.

Typically, each gain stage can provide by up to 10dB gain, therefore multiple gain stages are needed to have larger gain amplifier.

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PLL & xCO

Phased Locked Loop, PLL and Voltage Control Oscillator, VCO are part of any ASIC whether it is analog, mixed signal, or digital circuits.

PLL and VCO provide Local Oscillator, LO functionality for any legacy Heterodyne and Homodyne radio front end.

PLL and Numerical Control Oscillator, NCO provide clock functionality for mixed signal and digital circuits.

In radio front end the PLL  and VCO phase noise contribute to noise budget and overall RF impairments of the radio which impact SNR.

Poor phase noise could desensitize and/or reduce dynamic range of the receiver.

Aperture jitter impacts Software Defined Radio, SDR SNR.

Jitter is time domain signature of phase noise in frequency domain.

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ORTENGA is comprised of seasoned and skillful engineers who collaborate on innovative design in entrepreneurial environment to accomplish clients’ project.

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DPD challenges for UWB signals

Digital Pre Distortion, DPD, technique is widely used in mobile UE to linearize Power Amplifier, PA, output signal, such that it can be run into saturation mode without violating spurious and unwanted emissions while mitigating transmitter power efficiency, hence increasing the battery life time.

It turns out that spectral efficiency and power efficiency have contradictory constraints.

As we pack more bits into one symbol or alphabet, higher QAM, then the signal becomes more spectral efficient, bit per second per Hz, bps/Hz, hence more throughput.  As a result, the Peak power to Average Ratio, PAR, between each symbol can change significantly.  Higher PAR requires higher linearity PA, which in turns requires higher power consumption, hence less power efficiency.

5G is targeting higher BW or user datarates; up to 100MHz for FR1 and up to 4GHz for FR2 bands.

DPD techniques are based on pre distorting the desired signals prior to feeding in to the PA in such a way that the output is linear, i.e. the output is amplified version of the PA input signal.  This is possible when PA characteristic is well known in terms of AM2AM and AM2PM and utilized to predistort the desired input signal and feasible when PA characteristic is memoryless.

Memoryless refers to the fact that the output of PA does not depend on the previous input samples, only on the current sample.  PA can be memoryless up to a critical BW, which turns out to be around 20MHz.  In other words, PA is forgiving for less than 20MHz signal BW and has memory for signals over 20MHz.

For UWB, e.g. 5G mmW signals, DPD algorithms become run time computations.  That implies there is control loop which looks at the input and output signal of the PA and makes appropriate predistortion for every symbol to be transmitted.  The DPD control loop bandwidth becomes excessively large as the signal BW increases.

The following diagram illustrates the output of typical PA.

It can be seen that the first upper and lower adjacent channels are 3rd order intermodulation, whereas second upper and lower adjacent channels are 5th order intermodulation of the desired signal.  DPD job is to reduce these 3rd and 5th order intermodulation terms, significantly.

That implies, DPD has to have control loop bandwidth in such a way to resolve the first and second adjacent channels in frequency, total 5x BW.  By Nyquist sampling theorem that implies 10x BW of desired signal is required for DPD control loop.

Here is the summary of DPD challenges for 5G application, UWB:

  • Memory effect of PA
  • Run Time DSP computations of Predistortion signals
  • Control Loop BW of DPD

The question becomes, are there alternative ways to linearize the PA output?

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Fractional N PLL

Phased Lock Loop, better known as PLL are used to generate Local Oscillator, LO for radio front end or Clock for baseband circuitry.

Clock to ASIC is similar to Heart to Body which drives and organize timing responses of various organs.  Without Heart, the body cannot function, without Clock the ASIC cannot function.

Fractional N PLL aka Frac N PLL has 3 main advantages over Integer N PLL.

  1. Finer step frequency resolution relative to reference frequency
  2. One Frac N PLL can provide LO function for both Tx and Rx chain
  3. Agility to perform digitally controlled modulation

Needless to say, the above advantages do not come free, the Frac N PLL is much more complex in design and development.

In spite of that, the advantages overcome the trade off and are attractive in advanced ASIC.

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PLL Requirements for Terrestrial Radio and Radar Applications

PLL phase noise requirements are driven by in band, IB and out of band, OOB drivers.

IB driver is dominated by desired channel purity requirements which has budget in overall SNR.

OOB driver is dominated by adjacent channel, typically considered undesired, which has budget in dynamic range of the system.

Dynamic Range, DR of a radio is measure of how the radio can handle both small desired signal in presence of loud unwanted signal.

SNR and DR of any system whether it is Terrestrial Radio or Radar are of significant concern and differentiators for end users.

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UWB VCO

Ultra-Wide Band, UWB VCO are required in mmW and Radar applications.

Single VCO bandwidth circuitry is similar single element antenna bandwidth and can be quantified between 5 -10 % fractional bandwidth, FBW.

To increase the absolute bandwidth, the VCO frequency can be increased to 2x, 4x, or 8x of the required center frequency.

Consequently, post LO is frequency divided version of VCO.

Effectively that reduces the number of VCO for pulling full frequency range in UWB application, hence smaller ASIC die size, i.e., lower cost.

Octave or its multiple octave VCO resonance frequency helps with LO spurious free or purity of the desired spectrum.

These VCO provide mmW PLL functionality for mmW and Radar applications.

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Software Defined Radio, SDR

Radio Communications Systems have many applications such as; Broadcasting, BT, RFID, SATCOM, Terrestrial, and WiFi.

Furthermore, Radar Systems have many applications such as; short and long range, search and tracking radar.

Each application chooses tailored architecture which are typically requires one or two frequency conversions from RF to IF for receiver and vice versa IF to RF for transmitter chain.

The frequency conversion module is needed to convert the data from its original format to transmittable format which is in radio frequency regions.

Frequency conversion block adds significant design burden which means, it can only support one application.  Any system that can work without the frequency conversion block is highly desirable in both Radio Communication Systems and Radar Systems.

Removing the frequency conversion could be done if high datarate digitizer and waveform can be created that allows broad bandwidth.

In any architecture, ASIC plays the key role to achieve system requirements and performances.

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What is SDR and why it is used?

Software Defined Radio, SDR is an architecture which frequency conversion are removed from the radio front end.

That means, the radio front end is comprised of antenna, amplifier, and frequency selective filter components.

The objective for removing the frequency conversion block from radio front end is to alleviate the dependency of frequency conversion block on utilized desired signal waveform.

Various Radio Communications or Radar systems require dedicated waveform.

SDR allows the Radio Communications or Radar systems to become compatible to various desired signal waveforms.  Consequently, SDR is desirable architecture.

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What is RF Limiter and how it is used?

RF Limiters are used to protect sensitive electronic circuits, such as receivers’ front end, from strong undesired signal which can damage them.

Radio receivers are supposed to be very sensitive to very small desired signals of interest.

On the other hands, there are undesired signals which could be very large, 20 to 40 dB relative to the desired signals.

The receiver has job is to function in the presence of these types of undesired signals and yet survive that strong undesired signal.

This is particularly challenging when that desired signal is close to the top level of its dynamic range, consequently the strong undesired signal is way more than the level which receiver cannot function anymore.

Even though, we expect the receiver to survive this extreme radio environment condition.

The undesired signals could be due to un-intentional or intentional source.

Un-intentional source could be a radio station nearby or radar jammer which is trying to damage the radar system to avoid detection.

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Digital Direct Synthesizer, DDS

Digital Direct Synthesizer, DDS are digitally controlled frequency synthesizer source.

DDS have gain traction for many applications because of:

  • Excellent frequency resolution
  • Excellent frequency agility
  • Amplitude, frequency, and phase modulations capabilities
  • Digitally controlled
  • Size
  • Cost

DDS are utilized in many Arbitrary Wave Generators, AWG.

As high speed and wide bandwidth DAC becomes a reality, DDS finds more traction for highly integrated low-cost frequency synthesizer.

SDR architecture relies on DDS.

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RF Circuit Design is about Impedance Matching

When operating wavelength (frequency) is in order of electrical component size, KVL and KCL analysis fails as they are not applicable any longer, typically this is Radio Frequencies, RF.

Whether the architecture utilized is Heterodyne, Homodyne, or Software Defined Radio, SDR, there are LNA and PA in all these architectures.

LAN and PA designs are about impedance matching.  There is optimum yet distinct power gain, low thermal noise, high output power, and stable impedance regions.

Based on the design goals, the RF circuit designer needs to identify the above impedance and down select an optimum impedance for the input and output (and sometime inter-stage) in such a way that the overall performance meets stability and performance metrics.

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T/R Switch

Transmit and Receive, T/R Switches are utilized in radio front end system where Transmitting and Receiving occurs at a different time, e.g. TDD communication or radar systems.

TR switch typically resides right after antenna and requires high isolation between transmit and receive chain.

Needless to say, the switching speed has to be much better than the operating time interval.

Consequently, the switching time and isolation are the key driver in designing T/R Switch.

Silicon on Insulator, SoI is the process of the choice to meet both requirements.

In many system, the tolerance of the receive chain to withstand high power is another requirement which can be met via RF Limiter.

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Monolithic Microwave Integrated Circuit

Monolithic Microwave Integrated Circuit, MMIC is a circuit module which can be found in radio front ends of Radio Communications or Radar systems.

MMIC module could have Antenna, ASIC, or Algorithms via HW/FW/SW implementations.

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Reducing risk by aligning device physics with system and market requirements

 

Connecting device-level limits to system performance, yield, and time-to-market

Selecting the right semiconductor process for an RF or mixed-signal ASIC is fundamentally a tradeoff between frequency capability, gain requirements, yield, and cost. Two transistor figures of merit—fT and fmax —sit at the center of this decision.

Understanding fT and fmax

  • fT (Transition Frequency)
    fT is the frequency at which the transistor’s current gain falls to unity (0 dB). Beyond this point, the device no longer provides current gain.
  • fmax (Maximum Oscillation Frequency)
    fmax is the frequency at which the transistor’s unilateral power gain becomes unity (0 dB). Beyond f<sub>max</sub>, the device cannot deliver power gain.

Different RF and mmWave circuits rely on current gain, voltage gain, or power gain, making both fT and fmax critical—depending on the application.

Frequency Scaling and Gain Roll-Off

As operating frequency increases, required transistor performance rises accordingly. For any given semiconductor process, gain rolls off at approximately:

  • –6 dB per octave, or
  • –20 dB per decade

This fundamental behavior limits how far a given technology node can be pushed and directly influences process down-selection.

Silicon CMOS: Cost and Scale Advantages

In silicon CMOS processes, fT is a key technical driver, but it must be evaluated alongside cost.

ASIC cost is strongly tied to wafer economics, including:

  • Wafer diameter
  • Process complexity
  • Number of lithography masks

Larger wafers yield more dies per wafer, lowering the cost per die. Modern CMOS fabs routinely process wafers up to 300 mm (12”), with some advanced lines approaching even larger effective production formats. This scale advantage makes CMOS highly attractive for cost-sensitive, high-volume applications.

III–V Compound Semiconductors: Performance First

At higher RF and mmWave frequencies, silicon reaches its practical limits. Applications demanding extreme RF performance often require III–V compound semiconductor processes with much higher fT and fmax, such as:

  • GaAs
  • GaN
  • InP

These technologies support superior gain, breakdown voltage, and power density but come with important tradeoffs:

  • Smaller wafer sizes (typically up to ~8”)
  • Fewer qualified fabs worldwide
  • Higher per-die cost

As a result, III–V processes are commonly reserved for less cost-sensitive, performance-driven markets, including:

  • Advanced radio systems
  • Radar
  • Space and SATCOM
  • Specialized or custom RF front ends

Yield, Test, and Packaging: The Hidden Cost Drivers

Beyond wafer cost, total ASIC cost is heavily influenced by:

  • Wafer yield, driven by process maturity and circuit robustness
  • Wafer probe test time
  • Packaged device test time
  • Package selection, which can represent a significant fraction of total cost

Yield, in particular, depends not only on the foundry process but also on circuit topology, layout discipline, and tolerance to process variation—areas where design experience has an outsized impact on commercial success.

From Device Physics to Product Success

Choosing the optimal semiconductor process is not about maximizing fT or fmax in isolation. It requires a system-level understanding of:

  • Required gain type (current, voltage, or power)
  • Operating frequency and bandwidth
  • Cost targets and production volume
  • Yield and test strategy
  • Long-term product scalability

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ORTENGA helps companies navigate these tradeoffs from silicon to system, ensuring that transistor-level decisions align with product-level outcomes.

ORTENGA brings seasoned engineering expertise across:

  • Autonomous automotive
  • SATCOM and space systems
  • Radar
  • Smart city infrastructure
  • Wi-Fi and mobile terrestrial radio

Our network spans Antenna, ASIC, Algorithm, Hardware, Firmware, and Software engineering, enabling predictable execution—from process selection through product delivery.

ORTENGA aligns transistor physics with system requirements and product economics.

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From Phase Noise to Dynamic Range: How PLLs Shape Radio and Radar

Why in-band and out-of-band phase noise must be architected from system requirements, not just silicon

Phase-locked loop (PLL) phase noise requirements in terrestrial radio and radar systems are driven by in-band (IB) and out-of-band (OOB) considerations.

In-band (IB) phase noise is primarily dictated by desired channel purity. Its impact is directly budgeted within the overall signal-to-noise ratio (SNR), influencing demodulation accuracy, bit-error rate, and detection sensitivity.

Out-of-band (OOB) phase noise is dominated by adjacent and nearby undesired signals. These components stress the dynamic range (DR) of the system by raising the effective noise floor in the presence of strong blockers.

Dynamic range describes a radio or radar system’s ability to reliably detect weak desired signals while simultaneously tolerating strong unwanted interferers. It is a critical performance metric for both terrestrial communication and radar platforms.

Together, SNR and DR are foundational system-level differentiators. They define real-world performance, robustness, and ultimately user experience—often more than peak data rate or raw output power.

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From Wavelength to Impedance: Why RF Design Is an Impedance Problem, Not a Schematic Problem

How Distributed Effects, Matching Tradeoffs, and Stability Define Real RF Performance

When the operating wavelength becomes comparable to circuit dimensions, classical circuit assumptions break down. At radio frequencies (RF), lumped-element analysis based on KVL and KCL no longer tells the full story. Distributed effects dominate, parasitics become first-order contributors, and impedance—not schematics—becomes the governing design variable.

This is why RF systems often fail in ways that are difficult to diagnose. A schematic can be “correct,” simulations can converge, and yet measured performance still misses noise figure, gain, linearity, or stability targets. The root cause is rarely a missing component—it is almost always an unexamined impedance tradeoff.

Regardless of architecture—heterodyne, homodyne, or software-defined radio (SDR)—every RF signal chain relies on low-noise amplifiers (LNAs) and power amplifiers (PAs). These blocks do not have a single optimal impedance. Instead, there are distinct impedance regions for:

  • Maximum available or transducer gain
  • Minimum noise figure
  • Maximum output power and efficiency
  • Conditional or unconditional stability

Critically, these regions do not coincide.

Effective RF design is therefore an exercise in compromise. The designer must identify these impedance regions and deliberately down-select input, output, and sometimes inter-stage impedances that balance performance, robustness, and manufacturability. This decision cannot be made at the schematic level alone—it requires system awareness and physical intuition.

This is where RF projects often encounter hidden risk. Many designs optimize for gain or noise in isolation, unintentionally pushing the circuit closer to instability, compression, or sensitivity to process and layout variation. These issues may not surface until first silicon, OTA testing, or field deployment—when fixes become expensive and schedules slip.

ORTENGA’s RF audit approach is designed to uncover these risks early. Rather than reviewing schematics in isolation, ORTENGA analyzes RF circuits through the lens of impedance trade spaces—examining how matching choices interact with device physics, bias conditions, layout parasitics, and system-level requirements. The goal is not to redesign blindly, but to expose where impedance decisions constrain or endanger system performance.

By auditing LNAs, PAs, and inter-stage networks at the impedance level, ORTENGA helps teams understand why a design behaves the way it does—and what tradeoffs must change to achieve predictable results. The outcome is clearer root cause identification, fewer design spins, and RF systems that perform as expected outside the simulator.

In RF, success is not determined by how clean the schematic looks. It is determined by whether impedance choices were made deliberately, with full awareness of their consequences.

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